[llvm] [RISCV] Rename PALUVINoVm->ZvkALUVINoVm. NFC (PR #182077)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 18 09:50:41 PST 2026
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/182077
OP_VE was originally named OP_P which is how these classes got P in their name. Replace P with Zvk.
>From 4ad71e394eaed42c24c624ab5e4e72b18d6da250 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 18 Feb 2026 09:47:55 -0800
Subject: [PATCH] [RISCV] Rename PALUVINoVm->ZvkALUVINoVm. NFC
OP_VE was originally named OP_P which is how these classes got
P in their name. Replace P with Zvk.
---
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 40 +++++++++++-----------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 9aae940476ae2..5c1a0fe06647c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -51,13 +51,13 @@ multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6>
}
// op vd, vs2, vs1
-class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class ZvkALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: VALUVVNoVm<funct6, opv, opcodestr> {
let Inst{6-0} = OPC_OP_VE.Value;
}
// op vd, vs2, vs1
-class PALUVVNoVmTernary<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class ZvkALUVVNoVmTernary<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVV<funct6, opv, (outs VR:$vd_wb),
(ins VR:$vd, VR:$vs2, VR:$vs1),
opcodestr, "$vd, $vs2, $vs1"> {
@@ -69,14 +69,14 @@ class PALUVVNoVmTernary<bits<6> funct6, RISCVVFormat opv, string opcodestr>
}
// op vd, vs2, imm
-class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype>
+class ZvkALUVINoVm<bits<6> funct6, string opcodestr, Operand optype>
: VALUVINoVm<funct6, opcodestr, optype> {
let Inst{6-0} = OPC_OP_VE.Value;
let Inst{14-12} = OPMVV.Value;
}
// op vd, vs2, imm where vd is also a source regardless of tail policy
-class PALUVINoVmBinary<bits<6> funct6, string opcodestr, Operand optype>
+class ZvkALUVINoVmBinary<bits<6> funct6, string opcodestr, Operand optype>
: RVInstIVI<funct6, (outs VR:$vd_wb),
(ins VR:$vd, VR:$vs2, optype:$imm),
opcodestr, "$vd, $vs2, $imm"> {
@@ -90,7 +90,7 @@ class PALUVINoVmBinary<bits<6> funct6, string opcodestr, Operand optype>
// op vd, vs2 (use vs1 as instruction encoding) where vd is also a source
// regardless of tail policy
-class PALUVs2NoVmBinary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
+class ZvkALUVs2NoVmBinary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
string opcodestr>
: RVInstVUnary<funct6, vs1, opv, (outs VR:$vd_wb), (ins VR:$vd, VR:$vs2),
opcodestr, "$vd, $vs2"> {
@@ -103,10 +103,10 @@ class PALUVs2NoVmBinary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
RISCVVFormat opv, string opcodestr> {
- def NAME # _VV : PALUVs2NoVmBinary<funct6_vv, vs1, opv, opcodestr # ".vv">,
+ def NAME # _VV : ZvkALUVs2NoVmBinary<funct6_vv, vs1, opv, opcodestr # ".vv">,
SchedBinaryMC<"WriteVAESMVV", "ReadVAESMVV", "ReadVAESMVV">;
let RVVConstraint = VS2Constraint in
- def NAME # _VS : PALUVs2NoVmBinary<funct6_vs, vs1, opv, opcodestr # ".vs">,
+ def NAME # _VS : ZvkALUVs2NoVmBinary<funct6_vs, vs1, opv, opcodestr # ".vs">,
SchedBinaryMC<"WriteVAESMVV", "ReadVAESMVV", "ReadVAESMVV">;
}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
@@ -141,29 +141,29 @@ let Predicates = [HasStdExtZvkb] in {
let ElementsDependOn = EltDepsVLMask in {
let Predicates = [HasStdExtZvkg] in {
- def VGHSH_VV : PALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">,
+ def VGHSH_VV : ZvkALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">,
SchedTernaryMC<"WriteVGHSHV", "ReadVGHSHV", "ReadVGHSHV",
"ReadVGHSHV">;
- def VGMUL_VV : PALUVs2NoVmBinary<0b101000, 0b10001, OPMVV, "vgmul.vv">,
+ def VGMUL_VV : ZvkALUVs2NoVmBinary<0b101000, 0b10001, OPMVV, "vgmul.vv">,
SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">;
} // Predicates = [HasStdExtZvkg]
let Predicates = [HasStdExtZvkgs], RVVConstraint = VS2Constraint in {
- def VGHSH_VS : PALUVVNoVmTernary<0b100011, OPMVV, "vghsh.vs">,
+ def VGHSH_VS : ZvkALUVVNoVmTernary<0b100011, OPMVV, "vghsh.vs">,
SchedTernaryMC<"WriteVGHSHV", "ReadVGHSHV", "ReadVGHSHV",
"ReadVGHSHV">;
- def VGMUL_VS : PALUVs2NoVmBinary<0b101001, 0b10001, OPMVV, "vgmul.vs">,
+ def VGMUL_VS : ZvkALUVs2NoVmBinary<0b101001, 0b10001, OPMVV, "vgmul.vs">,
SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">;
} // Predicates = [HasStdExtZvkgs]
let Predicates = [HasStdExtZvknhaOrZvknhb], RVVConstraint = Sha2Constraint in {
- def VSHA2CH_VV : PALUVVNoVmTernary<0b101110, OPMVV, "vsha2ch.vv">,
+ def VSHA2CH_VV : ZvkALUVVNoVmTernary<0b101110, OPMVV, "vsha2ch.vv">,
SchedTernaryMC<"WriteVSHA2CHV", "ReadVSHA2CHV", "ReadVSHA2CHV",
"ReadVSHA2CHV">;
- def VSHA2CL_VV : PALUVVNoVmTernary<0b101111, OPMVV, "vsha2cl.vv">,
+ def VSHA2CL_VV : ZvkALUVVNoVmTernary<0b101111, OPMVV, "vsha2cl.vv">,
SchedTernaryMC<"WriteVSHA2CLV", "ReadVSHA2CLV", "ReadVSHA2CLV",
"ReadVSHA2CLV">;
- def VSHA2MS_VV : PALUVVNoVmTernary<0b101101, OPMVV, "vsha2ms.vv">,
+ def VSHA2MS_VV : ZvkALUVVNoVmTernary<0b101101, OPMVV, "vsha2ms.vv">,
SchedTernaryMC<"WriteVSHA2MSV", "ReadVSHA2MSV", "ReadVSHA2MSV",
"ReadVSHA2MSV">;
} // Predicates = [HasStdExtZvknhaOrZvknhb]
@@ -173,25 +173,25 @@ let Predicates = [HasStdExtZvkned] in {
defm VAESDM : VAES_MV_V_S<0b101000, 0b101001, 0b00000, OPMVV, "vaesdm">;
defm VAESEF : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;
defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
- def VAESKF1_VI : PALUVINoVm<0b100010, "vaeskf1.vi", uimm5>,
+ def VAESKF1_VI : ZvkALUVINoVm<0b100010, "vaeskf1.vi", uimm5>,
SchedUnaryMC<"WriteVAESKF1V", "ReadVAESKF1V">;
- def VAESKF2_VI : PALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>,
+ def VAESKF2_VI : ZvkALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>,
SchedBinaryMC<"WriteVAESKF2V", "ReadVAESKF2V", "ReadVAESKF2V">;
let RVVConstraint = VS2Constraint in
- def VAESZ_VS : PALUVs2NoVmBinary<0b101001, 0b00111, OPMVV, "vaesz.vs">,
+ def VAESZ_VS : ZvkALUVs2NoVmBinary<0b101001, 0b00111, OPMVV, "vaesz.vs">,
SchedBinaryMC<"WriteVAESZV", "ReadVAESZV", "ReadVAESZV">;
} // Predicates = [HasStdExtZvkned]
let Predicates = [HasStdExtZvksed] in {
- def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", uimm5>,
+ def VSM4K_VI : ZvkALUVINoVm<0b100001, "vsm4k.vi", uimm5>,
SchedUnaryMC<"WriteVSM4KV", "ReadVSM4KV">;
defm VSM4R : VAES_MV_V_S<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">;
} // Predicates = [HasStdExtZvksed]
let Predicates = [HasStdExtZvksh], RVVConstraint = VS2Constraint in {
- def VSM3C_VI : PALUVINoVmBinary<0b101011, "vsm3c.vi", uimm5>,
+ def VSM3C_VI : ZvkALUVINoVmBinary<0b101011, "vsm3c.vi", uimm5>,
SchedBinaryMC<"WriteVSM3CV", "ReadVSM3CV", "ReadVSM3CV">;
- def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">,
+ def VSM3ME_VV : ZvkALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">,
SchedUnaryMC<"WriteVSM3MEV", "ReadVSM3MEV">;
} // Predicates = [HasStdExtZvksh]
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