[llvm] AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE (PR #179810)

[Petar Avramovic via llvm-commits]

================
@@ -1715,3 +1717,74 @@ void RegBankLegalizeHelper::applyMappingTrivial(MachineInstr &MI) {
     }
   }
 }
+
+bool RegBankLegalizeHelper::applyRegisterBanksINTRIN_IMAGE(MachineInstr &MI) {
+  const AMDGPU::RsrcIntrinsic *RSrcIntrin =
+      AMDGPU::lookupRsrcIntrinsic(AMDGPU::getIntrinsicID(MI));
+  assert(RSrcIntrin && RSrcIntrin->IsImage);
+
+  unsigned RsrcIdx = RSrcIntrin->RsrcArg;
+  const unsigned NumDefs = MI.getNumExplicitDefs();
+
+  // The reported argument index is relative to the IR intrinsic call arguments,
+  // so we need to shift by the number of defs and the intrinsic ID.
+  RsrcIdx += NumDefs + 1;
+
+  MachineBasicBlock *MBB = MI.getParent();
+  B.setInsertPt(*MBB, MBB->SkipPHIsAndLabels(std::next(MI.getIterator())));
+
+  // Defs(for image loads with return) are vgpr.
+  for (unsigned i = 0; i < NumDefs; ++i) {
+    const RegisterBank *RB = MRI.getRegBank(MI.getOperand(i).getReg());
+    if (RB == SgprRB) {
+      Register Reg = MI.getOperand(i).getReg();
+      Register NewVgprDst =
+          MRI.createVirtualRegister({VgprRB, MRI.getType(Reg)});
+      MI.getOperand(i).setReg(NewVgprDst);
+      buildReadAnyLane(B, Reg, NewVgprDst, RBI);
+    }
+  }
+
+  B.setInstr(MI);
+
+  // Register uses(before RsrcIdx) are vgpr.
+  for (unsigned i = 1; i < RsrcIdx; ++i) {
+    MachineOperand &Op = MI.getOperand(i);
+    if (!Op.isReg())
+      continue;
+
+    Register Reg = Op.getReg();
+    if (!Reg.isVirtual())
+      continue;
----------------
petar-avramovic wrote:

`$noreg` can be src operand, check AMDGPULegalizerInfo.cpp
`SrcOp.setReg(AMDGPU::NoRegister);`
here is one example
`%24:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, %29(<2 x s16>), %30(<2 x s16>), %31(<2 x s16>), %32(<2 x s16>), $noreg, $noreg, %0(<8 x s32>), %1(<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x s32>), addrspace 8)`

https://github.com/llvm/llvm-project/pull/179810