[llvm] [AArch64] Always print the PRFM operation name (PR #182035)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 18 06:49:14 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Kerry McLaughlin (kmclaughlin-arm)
<details>
<summary>Changes</summary>
When the encoding in the "Rt" field of the PRFM instruction maps to a
`<prfop>` value, the name of the prefetch operation should be printed
regardless of whether the associated feature (e.g. FEAT_PRFMSLC)
is available. If the feature is not available, the instruction is a nop.
All other encodings are printed as an immediate.
---
Patch is 43.91 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/182035.diff
23 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64SystemOperands.td (-6)
- (modified) llvm/test/MC/AArch64/armv8.9a-prfm-slc.s (+1-10)
- (modified) llvm/test/MC/AArch64/basic-a64-instructions.s (+6-6)
- (modified) llvm/test/MC/Disassembler/AArch64/armv8.9a-prfm-slc.txt (+1-9)
- (modified) llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt (+2-2)
- (modified) llvm/test/tools/llvm-mca/AArch64/A64FX/A64-basic-instructions.s (+3-3)
- (modified) llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s (+3-3)
- (modified) llvm/test/tools/llvm-mca/AArch64/Apple/Inputs/basic-instructions.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s (+2-2)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s (+3-3)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s (+3-3)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s (+3-3)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A57-basic-instructions.s (+2-2)
- (modified) llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-basic-instructions.s (+3-3)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/basic-instructions.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-basic-instructions.s (+2-2)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s (+2-2)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s (+2-2)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s (+2-2)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s (+2-2)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s (+2-2)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s (+2-2)
- (modified) llvm/test/tools/llvm-mca/AArch64/Olympus/basic-instructions.s (+3-3)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index d71aeb629bb3a..fbf14e88049e5 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -411,30 +411,24 @@ def : PRFM<"pld", 0b00, "l2", 0b01, "keep", 0b0>;
def : PRFM<"pld", 0b00, "l2", 0b01, "strm", 0b1>;
def : PRFM<"pld", 0b00, "l3", 0b10, "keep", 0b0>;
def : PRFM<"pld", 0b00, "l3", 0b10, "strm", 0b1>;
-let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in {
def : PRFM<"pld", 0b00, "slc", 0b11, "keep", 0b0>;
def : PRFM<"pld", 0b00, "slc", 0b11, "strm", 0b1>;
-}
def : PRFM<"pli", 0b01, "l1", 0b00, "keep", 0b0>;
def : PRFM<"pli", 0b01, "l1", 0b00, "strm", 0b1>;
def : PRFM<"pli", 0b01, "l2", 0b01, "keep", 0b0>;
def : PRFM<"pli", 0b01, "l2", 0b01, "strm", 0b1>;
def : PRFM<"pli", 0b01, "l3", 0b10, "keep", 0b0>;
def : PRFM<"pli", 0b01, "l3", 0b10, "strm", 0b1>;
-let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in {
def : PRFM<"pli", 0b01, "slc", 0b11, "keep", 0b0>;
def : PRFM<"pli", 0b01, "slc", 0b11, "strm", 0b1>;
-}
def : PRFM<"pst", 0b10, "l1", 0b00, "keep", 0b0>;
def : PRFM<"pst", 0b10, "l1", 0b00, "strm", 0b1>;
def : PRFM<"pst", 0b10, "l2", 0b01, "keep", 0b0>;
def : PRFM<"pst", 0b10, "l2", 0b01, "strm", 0b1>;
def : PRFM<"pst", 0b10, "l3", 0b10, "keep", 0b0>;
def : PRFM<"pst", 0b10, "l3", 0b10, "strm", 0b1>;
-let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in {
def : PRFM<"pst", 0b10, "slc", 0b11, "keep", 0b0>;
def : PRFM<"pst", 0b10, "slc", 0b11, "strm", 0b1>;
-}
def : PRFM<"ir", 0b11, "", 0b00, "", 0b0>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AArch64/armv8.9a-prfm-slc.s b/llvm/test/MC/AArch64/armv8.9a-prfm-slc.s
index b7af572e81445..16544c496e0c1 100644
--- a/llvm/test/MC/AArch64/armv8.9a-prfm-slc.s
+++ b/llvm/test/MC/AArch64/armv8.9a-prfm-slc.s
@@ -1,32 +1,23 @@
-
-// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s --check-prefix=NO-SLC
+// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s
// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.9a < %s | FileCheck %s
// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v9.4a < %s | FileCheck %s
prfm pldslckeep, [x3]
// CHECK: prfm pldslckeep, [x3] // encoding: [0x66,0x00,0x80,0xf9]
-// NO-SLC: prfm #6, [x3]
prfm pldslcstrm, [x3]
// CHECK: prfm pldslcstrm, [x3] // encoding: [0x67,0x00,0x80,0xf9]
-// NO-SLC: prfm #7, [x3]
prfm plislckeep, [x3]
// CHECK: prfm plislckeep, [x3] // encoding: [0x6e,0x00,0x80,0xf9]
-// NO-SLC: prfm #14, [x3]
prfm plislcstrm, [x3]
// CHECK: prfm plislcstrm, [x3] // encoding: [0x6f,0x00,0x80,0xf9]
-// NO-SLC: prfm #15, [x3]
prfm pstslckeep, [x3]
// CHECK: prfm pstslckeep, [x3] // encoding: [0x76,0x00,0x80,0xf9]
-// NO-SLC: prfm #22, [x3]
prfm pstslcstrm, [x3]
// CHECK: prfm pstslcstrm, [x3] // encoding: [0x77,0x00,0x80,0xf9]
-// NO-SLC: prfm #23, [x3]
self:
prfm pldslckeep, self
// CHECK: prfm pldslckeep, self // encoding: [0bAAA00110,A,A,0xd8]
-// NO-SLC: prfm #6, self
prfm pldslckeep, [x3, x5]
// CHECK: prfm pldslckeep, [x3, x5] // encoding: [0x66,0x68,0xa5,0xf8]
-// NO-SLC: prfm #6, [x3, x5]
diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s
index b2ec5b6ac3678..093c09c67bacb 100644
--- a/llvm/test/MC/AArch64/basic-a64-instructions.s
+++ b/llvm/test/MC/AArch64/basic-a64-instructions.s
@@ -2226,11 +2226,11 @@ _func:
// CHECK: ldr x10, #-1048576 // encoding: [0x0a,0x00,0x80,0x58]
prfm pldl1strm, nowhere
- prfm #22, somewhere
+ prfm #25, somewhere
// CHECK: prfm pldl1strm, nowhere // encoding: [0bAAA00001,A,A,0xd8]
// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_aarch64_ldr_pcrel_imm19
-// CHECK: prfm #22, somewhere // encoding: [0bAAA10110,A,A,0xd8]
+// CHECK: prfm #25, somewhere // encoding: [0bAAA11001,A,A,0xd8]
// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_aarch64_ldr_pcrel_imm19
//------------------------------------------------------------------------------
@@ -2478,7 +2478,7 @@ _func:
prfm pstl2strm, [x2]
prfm pstl3keep, [x5]
prfm pstl3strm, [x6]
- prfm #15, [sp]
+ prfm #25, [sp]
// CHECK: prfm pldl1keep, [sp, #8] // encoding: [0xe0,0x07,0x80,0xf9]
// CHECK: prfm pldl1strm, [x3{{(, #0)?}}] // encoding: [0x61,0x00,0x80,0xf9]
// CHECK: prfm pldl2keep, [x5, #16] // encoding: [0xa2,0x08,0x80,0xf9]
@@ -2497,7 +2497,7 @@ _func:
// CHECK: prfm pstl2strm, [x2{{(, #0)?}}] // encoding: [0x53,0x00,0x80,0xf9]
// CHECK: prfm pstl3keep, [x5{{(, #0)?}}] // encoding: [0xb4,0x00,0x80,0xf9]
// CHECK: prfm pstl3strm, [x6{{(, #0)?}}] // encoding: [0xd5,0x00,0x80,0xf9]
-// CHECK: prfm #15, [sp{{(, #0)?}}] // encoding: [0xef,0x03,0x80,0xf9]
+// CHECK: prfm #25, [sp{{(, #0)?}}] // encoding: [0xf9,0x03,0x80,0xf9]
//// Floating-point versions
@@ -2597,7 +2597,7 @@ _func:
ldr x17, [x23, w9, sxtw]
ldr x18, [x22, w10, sxtw #0]
str d19, [x21, wzr, sxtw #3]
- prfm #6, [x0, x5]
+ prfm pldslckeep, [x0, x5]
// CHECK: ldr x3, [sp, x5] // encoding: [0xe3,0x6b,0x65,0xf8]
// CHECK: str x9, [x27, x6] // encoding: [0x69,0x6b,0x26,0xf8]
// CHECK: ldr d10, [x30, x7, lsl #3] // encoding: [0xca,0x7b,0x67,0xfc]
@@ -2610,7 +2610,7 @@ _func:
// CHECK: ldr x17, [x23, w9, sxtw] // encoding: [0xf1,0xca,0x69,0xf8]
// CHECK: ldr x18, [x22, w10, sxtw] // encoding: [0xd2,0xca,0x6a,0xf8]
// CHECK: str d19, [x21, wzr, sxtw #3] // encoding: [0xb3,0xda,0x3f,0xfc]
-// CHECK: prfm #6, [x0, x5{{(, lsl #0)?}}] // encoding: [0x06,0x68,0xa5,0xf8]
+// CHECK: prfm pldslckeep, [x0, x5{{(, lsl #0)?}}] // encoding: [0x06,0x68,0xa5,0xf8]
ldr q3, [sp, x5]
ldr q9, [x27, x6, lsl #0]
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.9a-prfm-slc.txt b/llvm/test/MC/Disassembler/AArch64/armv8.9a-prfm-slc.txt
index 8e06ca4d7d237..6bb7c59ac3b05 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.9a-prfm-slc.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.9a-prfm-slc.txt
@@ -1,35 +1,27 @@
-// RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s --check-prefix=NO-SLC
+// RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s
// RUN: llvm-mc -triple aarch64 -disassemble -mattr=+v8.9a < %s | FileCheck %s
// RUN: llvm-mc -triple aarch64 -disassemble -mattr=+v9.4a < %s | FileCheck %s
[0x66,0x00,0x80,0xf9]
// CHECK: prfm pldslckeep, [x3]
-// NO-SLC: prfm #6, [x3]
[0x67,0x00,0x80,0xf9]
// CHECK: prfm pldslcstrm, [x3]
-// NO-SLC: prfm #7, [x3]
[0x6e,0x00,0x80,0xf9]
// CHECK: prfm plislckeep, [x3]
-// NO-SLC: prfm #14, [x3]
[0x6f,0x00,0x80,0xf9]
// CHECK: prfm plislcstrm, [x3]
-// NO-SLC: prfm #15, [x3]
[0x76,0x00,0x80,0xf9]
// CHECK: prfm pstslckeep, [x3]
-// NO-SLC: prfm #22, [x3]
[0x77,0x00,0x80,0xf9]
// CHECK: prfm pstslcstrm, [x3]
-// NO-SLC: prfm #23, [x3]
[0x06,0x00,0x00,0xd8]
// CHECK: prfm pldslckeep, #0
-// NO-SLC: prfm #6, #0
[0x66,0x68,0xa5,0xf8]
// CHECK: prfm pldslckeep, [x3, x5]
-// NO-SLC: prfm #6, [x3, x5]
diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
index 5ffabfc692ad1..aa69236ef6fc4 100644
--- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
+++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -1894,9 +1894,9 @@
0x00 0x00 0x80 0x9c
# CHECK: prfm pldl1strm, #0
-# CHECK: prfm #22, #0
+# CHECK: prfm #25, #0
0x01 0x00 0x00 0xd8
-0x16 0x00 0x00 0xd8
+0x19 0x00 0x00 0xd8
#------------------------------------------------------------------------------
# Load/store exclusive
diff --git a/llvm/test/tools/llvm-mca/AArch64/A64FX/A64-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/A64FX/A64-basic-instructions.s
index f63d03b157364..f3ba9e181af3a 100644
--- a/llvm/test/tools/llvm-mca/AArch64/A64FX/A64-basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/A64FX/A64-basic-instructions.s
@@ -844,7 +844,7 @@ ldr s0, #8
ldr d0, #1048572
ldr q0, #-1048576
prfm pldl1strm, #0
-prfm #22, #0
+prfm #25, #0
#------------------------------------------------------------------------------
# Load/store exclusive
@@ -2106,7 +2106,7 @@ drps
# CHECK-NEXT: 1 5 1.00 * ldr d0, #1048572
# CHECK-NEXT: 1 5 1.00 * ldr q0, #-1048576
# CHECK-NEXT: 1 0 0.50 U prfm pldl1strm, #0
-# CHECK-NEXT: 1 0 0.50 U prfm #22, #0
+# CHECK-NEXT: 1 0 0.50 U prfm #25, #0
# CHECK-NEXT: 2 5 1.00 * * U stxrb w18, w8, [sp]
# CHECK-NEXT: 2 5 1.00 * * U stxrh w24, w15, [x16]
# CHECK-NEXT: 2 5 1.00 * * U stxr w5, w6, [x17]
@@ -3285,7 +3285,7 @@ drps
# CHECK-NEXT: - - 1.00 - - - - - ldr d0, #1048572
# CHECK-NEXT: - - 1.00 - - - - - ldr q0, #-1048576
# CHECK-NEXT: - 0.50 0.50 - - - - - prfm pldl1strm, #0
-# CHECK-NEXT: - 0.50 0.50 - - - - - prfm #22, #0
+# CHECK-NEXT: - 0.50 0.50 - - - - - prfm #25, #0
# CHECK-NEXT: - 1.00 1.00 - - - - - stxrb w18, w8, [sp]
# CHECK-NEXT: - 1.00 1.00 - - - - - stxrh w24, w15, [x16]
# CHECK-NEXT: - 1.00 1.00 - - - - - stxr w5, w6, [x17]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s
index 7dd05eb50085c..062a77883d741 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s
@@ -844,7 +844,7 @@ ldr s0, #8
ldr d0, #1048572
ldr q0, #-1048576
prfm pldl1strm, #0
-prfm #22, #0
+prfm #25, #0
#------------------------------------------------------------------------------
# Load/store exclusive
@@ -2106,7 +2106,7 @@ drps
# CHECK-NEXT: 1 3 0.50 * ldr d0, #1048572
# CHECK-NEXT: 1 3 0.50 * ldr q0, #-1048576
# CHECK-NEXT: 1 1 0.50 U prfm pldl1strm, #0
-# CHECK-NEXT: 1 1 0.50 U prfm #22, #0
+# CHECK-NEXT: 1 1 0.50 U prfm #25, #0
# CHECK-NEXT: 2 4 0.50 * * U stxrb w18, w8, [sp]
# CHECK-NEXT: 2 4 0.50 * * U stxrh w24, w15, [x16]
# CHECK-NEXT: 2 4 0.50 * * U stxr w5, w6, [x17]
@@ -3289,7 +3289,7 @@ drps
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr d0, #1048572
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr q0, #-1048576
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - prfm pldl1strm, #0
-# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - prfm #22, #0
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - prfm #25, #0
# CHECK-NEXT: - - - - - 0.50 0.50 0.50 0.50 - - - stxrb w18, w8, [sp]
# CHECK-NEXT: - - - - - 0.50 0.50 0.50 0.50 - - - stxrh w24, w15, [x16]
# CHECK-NEXT: - - - - - 0.50 0.50 0.50 0.50 - - - stxr w5, w6, [x17]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Apple/Inputs/basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Apple/Inputs/basic-instructions.s
index f0a7bdfe1fa4b..48254ad76b968 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Apple/Inputs/basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Apple/Inputs/basic-instructions.s
@@ -881,7 +881,7 @@ ldr s0, #8
ldr d0, #1048572
ldr q0, #-1048576
prfm pldl1strm, #0
-prfm #22, #0
+prfm #25, #0
#------------------------------------------------------------------------------
# Load/store exclusive
diff --git a/llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s
index d273b4bba15d6..e8f0858dc7382 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s
@@ -784,7 +784,7 @@
# CHECK-NEXT: 1 4 0.50 * ldr d0, #1048572
# CHECK-NEXT: 1 4 0.50 * ldr q0, #-1048576
# CHECK-NEXT: 1 4 0.50 U prfm pldl1strm, #0
-# CHECK-NEXT: 1 4 0.50 U prfm #22, #0
+# CHECK-NEXT: 1 4 0.50 U prfm #25, #0
# CHECK-NEXT: 2 8 1.00 * * U stxrb w18, w8, [sp]
# CHECK-NEXT: 2 8 1.00 * * U stxrh w24, w15, [x16]
# CHECK-NEXT: 2 8 1.00 * * U stxr w5, w6, [x17]
@@ -2055,7 +2055,7 @@
# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - ldr d0, #1048572
# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - ldr q0, #-1048576
# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - prfm pldl1strm, #0
-# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - prfm #22, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - prfm #25, #0
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - - - - - stxrb w18, w8, [sp]
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - - - - - stxrh w24, w15, [x16]
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - - - - - stxr w5, w6, [x17]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s
index 35b5d5b2ce435..434b0d53820a5 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s
@@ -844,7 +844,7 @@ ldr s0, #8
ldr d0, #1048572
ldr q0, #-1048576
prfm pldl1strm, #0
-prfm #22, #0
+prfm #25, #0
#------------------------------------------------------------------------------
# Load/store exclusive
@@ -2106,7 +2106,7 @@ drps
# CHECK-NEXT: 1 4 1.00 * ldr d0, #1048572
# CHECK-NEXT: 1 4 1.00 * ldr q0, #-1048576
# CHECK-NEXT: 1 4 1.00 U prfm pldl1strm, #0
-# CHECK-NEXT: 1 4 1.00 U prfm #22, #0
+# CHECK-NEXT: 1 4 1.00 U prfm #25, #0
# CHECK-NEXT: 2 5 2.00 * * U stxrb w18, w8, [sp]
# CHECK-NEXT: 2 5 2.00 * * U stxrh w24, w15, [x16]
# CHECK-NEXT: 2 5 2.00 * * U stxr w5, w6, [x17]
@@ -3286,7 +3286,7 @@ drps
# CHECK-NEXT: - - - 1.00 - - - - - ldr d0, #1048572
# CHECK-NEXT: - - - 1.00 - - - - - ldr q0, #-1048576
# CHECK-NEXT: - - - 1.00 - - - - - prfm pldl1strm, #0
-# CHECK-NEXT: - - - 1.00 - - - - - prfm #22, #0
+# CHECK-NEXT: - - - 1.00 - - - - - prfm #25, #0
# CHECK-NEXT: - - - 2.00 - - - - - stxrb w18, w8, [sp]
# CHECK-NEXT: - - - 2.00 - - - - - stxrh w24, w15, [x16]
# CHECK-NEXT: - - - 2.00 - - - - - stxr w5, w6, [x17]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s
index 8a5df91ad7973..72651d01adcfd 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s
@@ -844,7 +844,7 @@ ldr s0, #8
ldr d0, #1048572
ldr q0, #-1048576
prfm pldl1strm, #0
-prfm #22, #0
+prfm #25, #0
#------------------------------------------------------------------------------
# Load/store exclusive
@@ -2106,7 +2106,7 @@ drps
# CHECK-NEXT: 1 2 0.50 * ldr d0, #1048572
# CHECK-NEXT: 1 2 0.50 * ldr q0, #-1048576
# CHECK-NEXT: 1 2 0.50 U prfm pldl1strm, #0
-# CHECK-NEXT: 1 2 0.50 U prfm #22, #0
+# CHECK-NEXT: 1 2 0.50 U prfm #25, #0
# CHECK-NEXT: 2 3 1.00 * * U stxrb w18, w8, [sp]
# CHECK-NEXT: 2 3 1.00 * * U stxrh w24, w15, [x16]
# CHECK-NEXT: 2 3 1.00 * * U stxr w5, w6, [x17]
@@ -3291,7 +3291,7 @@ drps
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - ldr d0, #1048572
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - ldr q0, #-1048576
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - prfm pldl1strm, #0
-# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - prfm #22, #0
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - prfm #25, #0
# CHECK-NEXT: - - - - - 0.50 1.50 - - - - - - - stxrb w18, w8, [sp]
# CHECK-NEXT: - - - - - 0.50 1.50 - - - - - - - stxrh w24, w15, [x16]
# CHECK-NEXT: - - - - - 0.50 1.50 - - - - - - - stxr w5, w6, [x17]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s
index 9ad48f4f4065c..b0bffbf29bd38 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s
@@ -844,7 +844,7 @@ ldr s0, #8
ldr d0, #1048572
ldr q0, #-1048576
prfm pldl1strm, #0
-prfm #22, #0
+prfm #25, #0
#------------------------------------------------------------------------------
# Load/store exclusive
@@ -2106,7 +2106,7 @@ drps
# CHECK-NEXT: 1 3 1.00 * ldr d0, #1048572
# CHECK-NEXT: 1 3 1.00 * ldr q0, #-1048576
# CHECK-NEXT: 1 3 1.00 U prfm pldl1strm, #0
-# CHECK-NEXT: 1 3 ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/182035
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