[llvm] [AArch64] Add bfloat patterns for `partial_reduce_fmla` (PR #181982)

[Paul Walker via llvm-commits]

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@@ -2414,6 +2422,10 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
                               MVT::getVectorVT(MVT::f16, NumElts * 2), Custom);
   }
 
+  if (Subtarget->hasBF16() && VT == MVT::v4f32)
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paulwalker-arm wrote:

This might already be covered but I'll preempt with please remember the current "don't introduce potentially faulting behaviour across inactive lanes" requirement for SVE operations.

https://github.com/llvm/llvm-project/pull/181982