[llvm] [WIP][AMDGPU] Coverity fixes (PR #182013)
Rafał Rudnicki via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 18 05:05:24 PST 2026
https://github.com/bratpiorka updated https://github.com/llvm/llvm-project/pull/182013
>From b14e0ccdbe2099e878ad802d513cb1384ad98347 Mon Sep 17 00:00:00 2001
From: Rafal Rudnicki <rafal.rudnicki at intel.com>
Date: Wed, 18 Feb 2026 13:33:14 +0100
Subject: [PATCH] x
---
llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp | 2 +-
.../Target/AMDGPU/AMDGPULowerVGPREncoding.cpp | 2 +-
llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp | 5 +-
.../AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp | 3 +-
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 140 ++++++++++--------
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 10 +-
6 files changed, 91 insertions(+), 71 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
index b86a4ea7f384d..e13931a43a2f3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
@@ -1234,7 +1234,7 @@ static unsigned inlineAsmGetNumRequiredAGPRs(const InlineAsm *IA,
for (StringRef Code : CI.Codes) {
unsigned RegCount = 0;
- if (Code.starts_with("a")) {
+ if (Ty && Code.starts_with("a")) {
// Virtual register, compute number of registers based on the type.
//
// We ought to be going through TargetLowering to get the number of
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
index f4872ec63f7c3..b4595f16e3628 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
@@ -260,7 +260,7 @@ void AMDGPULowerVGPREncoding::computeMode(ModeTy &NewMode, MachineInstr &MI,
// Skip tied uses of src2 of VOP2, these will be handled along with defs and
// only vdst bit affects these operands. We cannot skip tied uses of VOP3,
// these uses are real even if must match the vdst.
- if (Ops[I] == AMDGPU::OpName::src2 && !Op->isDef() && Op->isTied() &&
+ if (Ops[I] == AMDGPU::OpName::src2 && Op && !Op->isDef() && Op->isTied() &&
(SIInstrInfo::isVOP2(MI) ||
(SIInstrInfo::isVOP3(MI) &&
TII->hasVALU32BitEncoding(MI.getOpcode()))))
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
index fc408aa30dd87..5cc18645918a8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
@@ -246,7 +246,10 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
if (MCOpcode == -1) {
LLVMContext &C = MI->getMF()->getFunction().getContext();
C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
- "a target-specific version: " + Twine(MI->getOpcode()));
+ "a target-specific version: " +
+ Twine(MI->getOpcode()));
+ MI->print(errs());
+ return;
}
OutMI.setOpcode(MCOpcode);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp b/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
index 7a5db42c7a89a..931a2854c54f9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
@@ -205,7 +205,8 @@ bool AMDGPURewriteAGPRCopyMFMAImpl::recomputeRegClassExceptRewritable(
if (!NewRC || NewRC == OldRC) {
LLVM_DEBUG(dbgs() << "User of " << printReg(Reg, &TRI)
<< " cannot be reassigned to "
- << TRI.getRegClassName(NewRC) << ": " << *MI);
+ << (NewRC ? TRI.getRegClassName(NewRC) : "NULL")
+ << ": " << *MI);
return false;
}
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 4aa4083b6c2ab..e6eb5fa7a08a2 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -140,8 +140,8 @@ void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
}
void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
printU32ImmOperand(MI, OpNo, STI, O);
}
@@ -179,8 +179,9 @@ void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
if (Imm & CPol::GLC)
O << ((AMDGPU::isGFX940(STI) &&
- !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0"
- : " glc");
+ !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD))
+ ? " sc0"
+ : " glc");
if (Imm & CPol::SLC)
O << (AMDGPU::isGFX940(STI) ? " nt" : " slc");
if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
@@ -281,7 +282,8 @@ void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
}
void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O) {
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
if (STI.hasFeature(AMDGPU::FeatureR128A16))
printNamedBit(MI, OpNo, O, "a16");
else
@@ -290,8 +292,7 @@ void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
- raw_ostream &O) {
-}
+ raw_ostream &O) {}
void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
const MCSubtargetInfo &STI,
@@ -299,7 +300,7 @@ void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
using namespace llvm::AMDGPU::MTBUFFormat;
int OpNo =
- AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
+ AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
assert(OpNo != -1);
unsigned Val = MI->getOperand(OpNo).getImm();
@@ -421,7 +422,8 @@ void AMDGPUInstPrinter::printRegOperand(MCRegister Reg, unsigned Opc,
}
void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O) {
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
auto Opcode = MI->getOpcode();
auto Flags = MII.get(Opcode).TSFlags;
if (OpNo == 0) {
@@ -444,7 +446,8 @@ void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
// Print default vcc/vcc_lo operand.
switch (Opcode) {
- default: break;
+ default:
+ break;
case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
@@ -482,7 +485,8 @@ void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
}
void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O) {
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
O << " ";
else
@@ -678,8 +682,7 @@ bool AMDGPUInstPrinter::printImmediateFloat32(uint32_t Imm,
O << "4.0";
else if (Imm == llvm::bit_cast<uint32_t>(-4.0f))
O << "-4.0";
- else if (Imm == 0x3e22f983 &&
- STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
+ else if (Imm == 0x3e22f983 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
O << "0.15915494";
else
return false;
@@ -745,8 +748,7 @@ void AMDGPUInstPrinter::printLiteral64(uint64_t Imm, raw_ostream &O,
}
void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
+ const MCSubtargetInfo &STI, raw_ostream &O) {
unsigned Imm = MI->getOperand(OpNo).getImm();
if (!Imm)
return;
@@ -917,7 +919,8 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
// Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
switch (MI->getOpcode()) {
- default: break;
+ default:
+ break;
case AMDGPU::V_CNDMASK_B32_e32_gfx10:
case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
@@ -956,15 +959,15 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
case AMDGPU::V_CNDMASK_B32_e32_vi:
- if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
- AMDGPU::OpName::src1))
+ if ((int)OpNo ==
+ AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::src1))
printDefaultVccOperand(OpNo == 0, STI, O);
break;
}
if (Desc.TSFlags & SIInstrFlags::MTBUF) {
int SOffsetIdx =
- AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
+ AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
assert(SOffsetIdx != -1);
if ((int)OpNo == SOffsetIdx)
printSymbolicFormat(MI, STI, O);
@@ -1041,21 +1044,21 @@ void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
// Print default vcc/vcc_lo operand of VOP2b.
switch (MI->getOpcode()) {
- default: break;
+ default:
+ break;
case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
- if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
- AMDGPU::OpName::src1))
+ if ((int)OpNo + 1 ==
+ AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::src1))
printDefaultVccOperand(OpNo == 0, STI, O);
break;
}
}
void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
+ const MCSubtargetInfo &STI, raw_ostream &O) {
if (!AMDGPU::isGFX10Plus(STI))
llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
@@ -1083,8 +1086,8 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
}
if (Imm <= DppCtrl::QUAD_PERM_LAST) {
O << "quad_perm:[";
- O << formatDec(Imm & 0x3) << ',';
- O << formatDec((Imm & 0xc) >> 2) << ',';
+ O << formatDec(Imm & 0x3) << ',';
+ O << formatDec((Imm & 0xc) >> 2) << ',';
O << formatDec((Imm & 0x30) >> 4) << ',';
O << formatDec((Imm & 0xc0) >> 6) << ']';
} else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
@@ -1184,14 +1187,29 @@ void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
unsigned Imm = MI->getOperand(OpNo).getImm();
switch (Imm) {
- case SdwaSel::BYTE_0: O << "BYTE_0"; break;
- case SdwaSel::BYTE_1: O << "BYTE_1"; break;
- case SdwaSel::BYTE_2: O << "BYTE_2"; break;
- case SdwaSel::BYTE_3: O << "BYTE_3"; break;
- case SdwaSel::WORD_0: O << "WORD_0"; break;
- case SdwaSel::WORD_1: O << "WORD_1"; break;
- case SdwaSel::DWORD: O << "DWORD"; break;
- default: llvm_unreachable("Invalid SDWA data select operand");
+ case SdwaSel::BYTE_0:
+ O << "BYTE_0";
+ break;
+ case SdwaSel::BYTE_1:
+ O << "BYTE_1";
+ break;
+ case SdwaSel::BYTE_2:
+ O << "BYTE_2";
+ break;
+ case SdwaSel::BYTE_3:
+ O << "BYTE_3";
+ break;
+ case SdwaSel::WORD_0:
+ O << "WORD_0";
+ break;
+ case SdwaSel::WORD_1:
+ O << "WORD_1";
+ break;
+ case SdwaSel::DWORD:
+ O << "DWORD";
+ break;
+ default:
+ llvm_unreachable("Invalid SDWA data select operand");
}
}
@@ -1224,10 +1242,17 @@ void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
O << "dst_unused:";
unsigned Imm = MI->getOperand(OpNo).getImm();
switch (Imm) {
- case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
- case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
- case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
- default: llvm_unreachable("Invalid SDWA dest_unused operand");
+ case DstUnused::UNUSED_PAD:
+ O << "UNUSED_PAD";
+ break;
+ case DstUnused::UNUSED_SEXT:
+ O << "UNUSED_SEXT";
+ break;
+ case DstUnused::UNUSED_PRESERVE:
+ O << "UNUSED_PRESERVE";
+ break;
+ default:
+ llvm_unreachable("Invalid SDWA dest_unused operand");
}
}
@@ -1293,7 +1318,7 @@ void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
}
}
-static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
+static bool allOpsDefaultValue(const int *Ops, int NumOps, int Mod,
bool IsPacked, bool HasDstSel) {
int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
@@ -1308,10 +1333,8 @@ static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
return true;
}
-void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
- StringRef Name,
- unsigned Mod,
- raw_ostream &O) {
+void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI, StringRef Name,
+ unsigned Mod, raw_ostream &O) {
unsigned Opc = MI->getOpcode();
int NumOps = 0;
int Ops[3];
@@ -1368,7 +1391,7 @@ void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
const bool IsPacked =
- MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
+ MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
return;
@@ -1386,8 +1409,7 @@ void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
}
void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
+ const MCSubtargetInfo &STI, raw_ostream &O) {
unsigned Opc = MI->getOpcode();
if (isCvt_F32_Fp8_Bf8_e64(Opc)) {
auto SrcMod =
@@ -1419,14 +1441,12 @@ void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
}
void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
+ const MCSubtargetInfo &STI, raw_ostream &O) {
printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
}
void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
+ const MCSubtargetInfo &STI, raw_ostream &O) {
printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
}
@@ -1565,8 +1585,8 @@ void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
}
void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
unsigned Chan = MI->getOperand(OpNum).getImm();
O << '.' << "xyzw"[Chan & 0x3];
}
@@ -1594,7 +1614,7 @@ void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
printRegularOperand(MI, OpNo, STI, O);
- O << ", ";
+ O << ", ";
printRegularOperand(MI, OpNo + 1, STI, O);
}
@@ -1674,13 +1694,11 @@ void AMDGPUInstPrinter::printWaitEvent(const MCInst *MI, unsigned OpNo,
O << EventName;
}
-static void printSwizzleBitmask(const uint16_t AndMask,
- const uint16_t OrMask,
- const uint16_t XorMask,
- raw_ostream &O) {
+static void printSwizzleBitmask(const uint16_t AndMask, const uint16_t OrMask,
+ const uint16_t XorMask, raw_ostream &O) {
using namespace llvm::AMDGPU::Swizzle;
- uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask;
+ uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask;
uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
O << "\"";
@@ -1745,7 +1763,7 @@ void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
} else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
- uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK;
+ uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK;
uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
if (AndMask == BITMASK_MAX && OrMask == 0 && llvm::popcount(XorMask) == 1) {
@@ -1766,9 +1784,7 @@ void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
} else {
uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
- if (GroupSize > 1 &&
- isPowerOf2_64(GroupSize) &&
- OrMask < GroupSize &&
+ if (GroupSize > 1 && isPowerOf2_64(GroupSize) && OrMask < GroupSize &&
XorMask == 0) {
O << "swizzle(" << IdSymbolic[ID_BROADCAST];
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 5b83574dee0c3..22a8de8946d62 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -11971,10 +11971,10 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
case Intrinsic::amdgcn_cooperative_atomic_store_8x16B: {
MemIntrinsicSDNode *MII = cast<MemIntrinsicSDNode>(Op);
SDValue Chain = Op->getOperand(0);
- SDValue Ptr = Op->getOperand(2);
- SDValue Val = Op->getOperand(3);
- return DAG.getAtomic(ISD::ATOMIC_STORE, DL, MII->getMemoryVT(), Chain, Val,
- Ptr, MII->getMemOperand());
+ SDValue Val = Op->getOperand(2);
+ SDValue Ptr = Op->getOperand(3);
+ return DAG.getAtomic(ISD::ATOMIC_STORE, DL, MII->getMemoryVT(), Chain, Ptr,
+ Val, MII->getMemOperand());
}
default: {
if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
@@ -18253,7 +18253,7 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
// Check for lossy scalar/vector conversions.
if (VT.isVector() && VT.getSizeInBits() != 32)
return std::pair(0U, nullptr);
- if (Idx < RC->getNumRegs())
+ if (RC && Idx < RC->getNumRegs())
return std::pair(RC->getRegister(Idx), RC);
return std::pair(0U, nullptr);
}
More information about the llvm-commits
mailing list