[llvm] [WIP][AMDGPU] Coverity fixes (PR #182013)
Rafał Rudnicki via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 18 05:01:11 PST 2026
https://github.com/bratpiorka created https://github.com/llvm/llvm-project/pull/182013
Coverity fixes
>From 76037f32c701bd0cfd939f1d5c6190362152f89b Mon Sep 17 00:00:00 2001
From: Rafal Rudnicki <rafal.rudnicki at intel.com>
Date: Wed, 18 Feb 2026 13:33:14 +0100
Subject: [PATCH] x
---
llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp | 2 +-
.../Target/AMDGPU/AMDGPULowerVGPREncoding.cpp | 6 +++---
llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp | 5 ++++-
.../AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp | 3 ++-
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 18 +++++++++---------
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 10 +++++-----
6 files changed, 24 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
index 821a7198e38c8..90a776d9d51a1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
@@ -1236,7 +1236,7 @@ static unsigned inlineAsmGetNumRequiredAGPRs(const InlineAsm *IA,
for (StringRef Code : CI.Codes) {
unsigned RegCount = 0;
- if (Code.starts_with("a")) {
+ if (Ty && Code.starts_with("a")) {
// Virtual register, compute number of registers based on the type.
//
// We ought to be going through TargetLowering to get the number of
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
index 0d89fc8819929..89a8b432d26d1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
@@ -257,7 +257,7 @@ void AMDGPULowerVGPREncoding::computeMode(ModeTy &NewMode, ModeTy &Mask,
// Skip tied uses of src2 of VOP2, these will be handled along with defs and
// only vdst bit affects these operands. We cannot skip tied uses of VOP3,
// these uses are real even if must match the vdst.
- if (Ops[I] == AMDGPU::OpName::src2 && !Op->isDef() && Op->isTied() &&
+ if (Ops[I] == AMDGPU::OpName::src2 && Op && !Op->isDef() && Op->isTied() &&
(SIInstrInfo::isVOP2(MI) ||
(SIInstrInfo::isVOP3(MI) &&
TII->hasVALU32BitEncoding(MI.getOpcode()))))
@@ -324,8 +324,8 @@ AMDGPULowerVGPREncoding::handleCoissue(MachineBasicBlock::instr_iterator I) {
MachineBasicBlock::instr_iterator Prev = std::prev(I);
auto isProgramStateSALU = [this](MachineInstr *MI) {
return TII->isBarrier(MI->getOpcode()) ||
- TII->isWaitcnt(MI || (SIInstrInfo::isProgramStateSALU(*MI) &&
- MI->getOpcode() != AMDGPU::S_SET_VGPR_MSB));
+ TII->isWaitcnt(SIInstrInfo::isProgramStateSALU(*MI) &&
+ MI->getOpcode() != AMDGPU::S_SET_VGPR_MSB);
};
if (!isProgramStateSALU(&*Prev))
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
index 99c1ab8d379d5..f1cb520d76d2e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
@@ -246,7 +246,10 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
if (MCOpcode == -1) {
LLVMContext &C = MI->getMF()->getFunction().getContext();
C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
- "a target-specific version: " + Twine(MI->getOpcode()));
+ "a target-specific version: " +
+ Twine(MI->getOpcode()));
+ MI->print(errs());
+ return;
}
OutMI.setOpcode(MCOpcode);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp b/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
index ffbb1c183ca9e..9b56ff35a6fff 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
@@ -205,7 +205,8 @@ bool AMDGPURewriteAGPRCopyMFMAImpl::recomputeRegClassExceptRewritable(
if (!NewRC || NewRC == OldRC) {
LLVM_DEBUG(dbgs() << "User of " << printReg(Reg, &TRI)
<< " cannot be reassigned to "
- << TRI.getRegClassName(NewRC) << ": " << *MI);
+ << (NewRC ? TRI.getRegClassName(NewRC) : "NULL")
+ << ": " << *MI);
return false;
}
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index b63d71dc2fde9..fc5fd3bb2cefb 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -1449,9 +1449,6 @@ void AMDGPUInstPrinter::printMatrixFMT(const MCInst *MI, unsigned OpNo,
O << " matrix_" << AorB << "_fmt:";
switch (Imm) {
- default:
- O << Imm;
- break;
case WMMA::MatrixFMT::MATRIX_FMT_FP8:
O << "MATRIX_FMT_FP8";
break;
@@ -1466,6 +1463,9 @@ void AMDGPUInstPrinter::printMatrixFMT(const MCInst *MI, unsigned OpNo,
break;
case WMMA::MatrixFMT::MATRIX_FMT_FP4:
O << "MATRIX_FMT_FP4";
+ break;
+ default:
+ O << Imm;
break;
}
}
@@ -1491,15 +1491,15 @@ void AMDGPUInstPrinter::printMatrixScale(const MCInst *MI, unsigned OpNo,
O << " matrix_" << AorB << "_scale:";
switch (Imm) {
- default:
- O << Imm;
- break;
case WMMA::MatrixScale::MATRIX_SCALE_ROW0:
O << "MATRIX_SCALE_ROW0";
break;
case WMMA::MatrixScale::MATRIX_SCALE_ROW1:
O << "MATRIX_SCALE_ROW1";
break;
+ default:
+ O << Imm;
+ break;
}
}
@@ -1524,9 +1524,6 @@ void AMDGPUInstPrinter::printMatrixScaleFmt(const MCInst *MI, unsigned OpNo,
O << " matrix_" << AorB << "_scale_fmt:";
switch (Imm) {
- default:
- O << Imm;
- break;
case WMMA::MatrixScaleFmt::MATRIX_SCALE_FMT_E8:
O << "MATRIX_SCALE_FMT_E8";
break;
@@ -1536,6 +1533,9 @@ void AMDGPUInstPrinter::printMatrixScaleFmt(const MCInst *MI, unsigned OpNo,
case WMMA::MatrixScaleFmt::MATRIX_SCALE_FMT_E4M3:
O << "MATRIX_SCALE_FMT_E4M3";
break;
+ default:
+ O << Imm;
+ break;
}
}
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 139e2d101a077..02675a5e40fc5 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -11684,10 +11684,10 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
case Intrinsic::amdgcn_cooperative_atomic_store_8x16B: {
MemIntrinsicSDNode *MII = cast<MemIntrinsicSDNode>(Op);
SDValue Chain = Op->getOperand(0);
- SDValue Ptr = Op->getOperand(2);
- SDValue Val = Op->getOperand(3);
- return DAG.getAtomic(ISD::ATOMIC_STORE, DL, MII->getMemoryVT(), Chain, Val,
- Ptr, MII->getMemOperand());
+ SDValue Val = Op->getOperand(2);
+ SDValue Ptr = Op->getOperand(3);
+ return DAG.getAtomic(ISD::ATOMIC_STORE, DL, MII->getMemoryVT(), Chain, Ptr,
+ Val, MII->getMemOperand());
}
default: {
if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
@@ -17885,7 +17885,7 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
// Check for lossy scalar/vector conversions.
if (VT.isVector() && VT.getSizeInBits() != 32)
return std::pair(0U, nullptr);
- if (Idx < RC->getNumRegs())
+ if (RC && Idx < RC->getNumRegs())
return std::pair(RC->getRegister(Idx), RC);
return std::pair(0U, nullptr);
}
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