[llvm] 10ccf11 - [Tablegen] Patch RegUnitIntervals Initialization (#181173)

[via llvm-commits]

Author: Ryan Mitchell
Date: 2026-02-18T12:09:48+01:00
New Revision: 10ccf11ebb79d43fd287e9de278413d5c5e85062

URL: https://github.com/llvm/llvm-project/commit/10ccf11ebb79d43fd287e9de278413d5c5e85062
DIFF: https://github.com/llvm/llvm-project/commit/10ccf11ebb79d43fd287e9de278413d5c5e85062.diff

LOG: [Tablegen] Patch RegUnitIntervals Initialization (#181173)

There were a few places it was missing some code-generation to properly
initialize it if enabled, and also it was missing the sentinel value.

Added: 
    

Modified: 
    llvm/test/TableGen/regunit-intervals.td
    llvm/utils/TableGen/RegisterInfoEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/test/TableGen/regunit-intervals.td b/llvm/test/TableGen/regunit-intervals.td
index a78f62836a7bc..c81c0f91eba7b 100644
--- a/llvm/test/TableGen/regunit-intervals.td
+++ b/llvm/test/TableGen/regunit-intervals.td
@@ -32,6 +32,9 @@ let Namespace = "Test" in {
 }
 
 // CHECK: extern const unsigned TestTargetRegUnitIntervals[][2] = {
+// Sentinel
+// CHECK-NEXT: { 0, 0 },
+// Real values
 // CHECK-NEXT: { 0, 1 },
 // CHECK-NEXT: { 1, 2 },
 // CHECK-NEXT: { 2, 3 },

diff  --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 02eec4aec3f40..1579c344a9c31 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1036,6 +1036,8 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, raw_ostream &MainOS,
   if (Target.getRegistersAreIntervals()) {
     OS << "extern const unsigned " << TargetName
        << "RegUnitIntervals[][2] = {\n";
+    // Add entry for NoRegister
+    OS << "  { 0, 0 },\n";
     for (const CodeGenRegister &Reg : Regs) {
       const auto &Units = Reg.getNativeRegUnits();
       if (Units.empty()) {
@@ -1138,7 +1140,10 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, raw_ostream &MainOS,
      << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, "
      << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, "
      << (llvm::size(SubRegIndices) + 1) << ",\n"
-     << TargetName << "RegEncodingTable);\n\n";
+     << TargetName << "RegEncodingTable, "
+     << (Target.getRegistersAreIntervals() ? TargetName + "RegUnitIntervals"
+                                           : "nullptr")
+     << ");\n\n";
 
   EmitRegMapping(OS, Regs, false);
 
@@ -1664,6 +1669,8 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS,
   OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
   OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
   OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
+  if (Target.getRegistersAreIntervals())
+    OS << "extern const unsigned " << TargetName << "RegUnitIntervals[][2];\n";
 
   EmitRegMappingTables(OS, Regs, true);
 
@@ -1689,7 +1696,11 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS,
      << "                     " << TargetName << "RegClassStrings,\n"
      << "                     " << TargetName << "SubRegIdxLists,\n"
      << "                     " << SubRegIndicesSize + 1 << ",\n"
-     << "                     " << TargetName << "RegEncodingTable);\n\n";
+     << "                     " << TargetName << "RegEncodingTable,\n"
+     << "                     "
+     << (Target.getRegistersAreIntervals() ? TargetName + "RegUnitIntervals"
+                                           : "nullptr")
+     << ");\n\n";
 
   EmitRegMapping(OS, Regs, true);