[llvm] [DAG] Improved ISD::SHL handling in isKnownToBeAPowerOfTwo (PR #181882)

[Aadarsh Keshri via llvm-commits]

================
@@ -4712,10 +4712,12 @@ bool SelectionDAG::isKnownToBeAPowerOfTwo(SDValue Val,
   case ISD::SHL: {
     // A left-shift of a constant one will have exactly one bit set because
     // shifting the bit off the end is undefined.
-    auto *C = isConstOrConstSplat(Val.getOperand(0));
+    auto *C = isConstOrConstSplat(Val.getOperand(0), DemandedElts);
     if (C && C->getAPIntValue() == 1)
       return true;
-    return isKnownToBeAPowerOfTwo(Val.getOperand(0), /*OrZero=*/false,
+    if (!(OrZero || isKnownNeverZero(Val, Depth)))
----------------
Aadarsh-Keshri wrote:

Sorry, I didn't think about time/space complexity while writing this patch.
I'll be careful from now on

https://github.com/llvm/llvm-project/pull/181882