[llvm] [RISCV] Set RVVConstraint = NoConstraint in tablegen classes with vm=1. NFC (PR #181960)
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Tue Feb 17 19:49:53 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
Our RVV base classes default to RVVConstraint = VMConstraint. We
should force it to NoConstraint in classes where we've explicitly
marked vm as being a constant rather than an operand. This avoids
needing to do it at a higher level in the class hierarchy.
---
Full diff: https://github.com/llvm/llvm-project/pull/181960.diff
4 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrFormats.td (+6)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoV.td (+9-2)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td (+7-3)
- (modified) llvm/test/MC/RISCV/rvv/zvkned.s (+12)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 9ecc2f60262c8..b17a5f1b772e3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -61,6 +61,12 @@ def InstFormatNDS_BRANCH_10 : InstFormat<27>;
def InstFormatOther : InstFormat<31>;
+// Indicates which operands cannot be the same as the Vd operand. This is used
+// by the assembler to provide some checking of the RVV overlap rules. We can't
+// check all overlap rules. Narrowing instructions allow overlap in the first
+// part of the register group, but not the later parts. We are not able to check
+// this in the assembler as we do not know how big the register group is since
+// that is controlled dynamically with vtype.
class RISCVVConstraint<bit VS2 = 0, bit VS1 = 0, bit VM = 0> {
bits<3> Value = {VM, VS1, VS2};
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index b8212e970aa38..9b75fa9282a19 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -514,6 +514,8 @@ class VALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
(ins VR:$vs2, VR:$vs1),
opcodestr, "$vd, $vs2, $vs1"> {
let vm = 1;
+
+ let RVVConstraint = NoConstraint;
}
// op vd, vs2, rs1, vm
@@ -546,6 +548,8 @@ class VALUVXNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
(ins VR:$vs2, GPR:$rs1),
opcodestr, "$vd, $vs2, $rs1"> {
let vm = 1;
+
+ let RVVConstraint = NoConstraint;
}
// op vd, vs2, imm, vm
@@ -568,6 +572,8 @@ class VALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5>
(ins VR:$vs2, optype:$imm),
opcodestr, "$vd, $vs2, $imm"> {
let vm = 1;
+
+ let RVVConstraint = NoConstraint;
}
// op vd, vs2, rs1, vm (Float)
@@ -1764,8 +1770,7 @@ let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress, ElementsDepend
defm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress, ElementsDependOn = EltDepsVLMask
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1,
- RVVConstraint = NoConstraint in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1 in {
// A future extension may relax the vector register alignment restrictions.
foreach n = [1, 2, 4, 8] in {
defvar vrc = !cast<VReg>(!if(!eq(n, 1), "VR", "VRM"#n));
@@ -1774,6 +1779,8 @@ foreach n = [1, 2, 4, 8] in {
VMVRSched<n> {
let Uses = [VTYPE];
let vm = 1;
+
+ let RVVConstraint = NoConstraint;
}
}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 3a5ddb8b2b994..9aae940476ae2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -64,6 +64,8 @@ class PALUVVNoVmTernary<bits<6> funct6, RISCVVFormat opv, string opcodestr>
let Constraints = "$vd = $vd_wb";
let vm = 1;
let Inst{6-0} = OPC_OP_VE.Value;
+
+ let RVVConstraint = NoConstraint;
}
// op vd, vs2, imm
@@ -82,6 +84,8 @@ class PALUVINoVmBinary<bits<6> funct6, string opcodestr, Operand optype>
let vm = 1;
let Inst{6-0} = OPC_OP_VE.Value;
let Inst{14-12} = OPMVV.Value;
+
+ let RVVConstraint = NoConstraint;
}
// op vd, vs2 (use vs1 as instruction encoding) where vd is also a source
@@ -93,11 +97,12 @@ class PALUVs2NoVmBinary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
let Constraints = "$vd = $vd_wb";
let vm = 1;
let Inst{6-0} = OPC_OP_VE.Value;
+
+ let RVVConstraint = NoConstraint;
}
multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
RISCVVFormat opv, string opcodestr> {
- let RVVConstraint = NoConstraint in
def NAME # _VV : PALUVs2NoVmBinary<funct6_vv, vs1, opv, opcodestr # ".vv">,
SchedBinaryMC<"WriteVAESMVV", "ReadVAESMVV", "ReadVAESMVV">;
let RVVConstraint = VS2Constraint in
@@ -135,7 +140,7 @@ let Predicates = [HasStdExtZvkb] in {
let ElementsDependOn = EltDepsVLMask in {
-let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {
+let Predicates = [HasStdExtZvkg] in {
def VGHSH_VV : PALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">,
SchedTernaryMC<"WriteVGHSHV", "ReadVGHSHV", "ReadVGHSHV",
"ReadVGHSHV">;
@@ -178,7 +183,6 @@ let Predicates = [HasStdExtZvkned] in {
} // Predicates = [HasStdExtZvkned]
let Predicates = [HasStdExtZvksed] in {
- let RVVConstraint = NoConstraint in
def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", uimm5>,
SchedUnaryMC<"WriteVSM4KV", "ReadVSM4KV">;
defm VSM4R : VAES_MV_V_S<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">;
diff --git a/llvm/test/MC/RISCV/rvv/zvkned.s b/llvm/test/MC/RISCV/rvv/zvkned.s
index bee3d74ee88dc..6bd2b14bc428b 100644
--- a/llvm/test/MC/RISCV/rvv/zvkned.s
+++ b/llvm/test/MC/RISCV/rvv/zvkned.s
@@ -68,6 +68,12 @@ vaeskf1.vi v10, v9, 31
# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
# CHECK-UNKNOWN: 8a9fa577 <unknown>
+vaeskf1.vi v0, v9, 1
+# CHECK-INST: vaeskf1.vi v0, v9, 1
+# CHECK-ENCODING: [0x77,0xa0,0x90,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 8a90a077 <unknown>
+
vaeskf2.vi v10, v9, 2
# CHECK-INST: vaeskf2.vi v10, v9, 2
# CHECK-ENCODING: [0x77,0x25,0x91,0xaa]
@@ -80,6 +86,12 @@ vaeskf2.vi v10, v9, 31
# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
# CHECK-UNKNOWN: aa9fa577 <unknown>
+vaeskf2.vi v0, v9, 2
+# CHECK-INST: vaeskf2.vi v0, v9, 2
+# CHECK-ENCODING: [0x77,0x20,0x91,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: aa912077 <unknown>
+
vaesz.vs v10, v9
# CHECK-INST: vaesz.vs v10, v9
# CHECK-ENCODING: [0x77,0xa5,0x93,0xa6]
``````````
</details>
https://github.com/llvm/llvm-project/pull/181960
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