[llvm] 75aa83c - [SDAG] foldSelectToABD - canonicalize compare of abd (#180952)

[via llvm-commits]

Author: DaKnig
Date: 2026-02-17T14:02:53Z
New Revision: 75aa83c0c035a7a10f0f48355c93858f003b8e4e

URL: https://github.com/llvm/llvm-project/commit/75aa83c0c035a7a10f0f48355c93858f003b8e4e
DIFF: https://github.com/llvm/llvm-project/commit/75aa83c0c035a7a10f0f48355c93858f003b8e4e.diff

LOG: [SDAG] foldSelectToABD - canonicalize compare of abd (#180952)

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/test/CodeGen/AArch64/arm64-vabs.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index adc197069f7c3..51fbe62b4aff0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12581,6 +12581,21 @@ SDValue DAGCombiner::foldSelectToABD(SDValue LHS, SDValue RHS, SDValue True,
   if (LegalOperations && !hasOperation(ABDOpc, VT))
     return SDValue();
 
+  // (setcc 0, b set???) --> (setcc b, 0, set???)
+  if (isZeroOrZeroSplat(LHS)) {
+    std::swap(LHS, RHS);
+    CC = ISD::getSetCCSwappedOperands(CC);
+  }
+
+  // (setcc (add nsw A, Const), 0, sets??) --> (setcc A, -Const, sets??)
+  SDValue A, B;
+  if (ISD::isSignedIntSetCC(CC) && LHS->getFlags().hasNoSignedWrap() &&
+      isZeroOrZeroSplat(RHS) && sd_match(LHS, m_Add(m_Value(A), m_Value(B))) &&
+      DAG.isConstantIntBuildVectorOrConstantInt(B)) {
+    RHS = DAG.getNegative(B, LHS, B.getValueType());
+    LHS = A;
+  }
+
   switch (CC) {
   case ISD::SETGT:
   case ISD::SETGE:

diff  --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index 4ceba23df55a8..d175247cca3d9 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -2165,3 +2165,51 @@ define <16 x i16> @uabd16b_i16_ext(<16 x i16> %aext, <16 x i8> %b) {
   %reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
   ret <16 x i16> %absel
 }
+
+
+define <4 x i32> @uabd_i32_select_const_lhs_add(<4 x i32> %a) {
+; CHECK-SD-LABEL: uabd_i32_select_const_lhs_add:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mvni.4s v1, #102
+; CHECK-SD-NEXT:    sabd.4s v0, v0, v1
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: uabd_i32_select_const_lhs_add:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    movi.4s v1, #103
+; CHECK-GI-NEXT:    mvni.4s v2, #102
+; CHECK-GI-NEXT:    add.4s v1, v0, v1
+; CHECK-GI-NEXT:    sub.4s v0, v2, v0
+; CHECK-GI-NEXT:    cmlt.4s v3, v1, #0
+; CHECK-GI-NEXT:    bif.16b v0, v1, v3
+; CHECK-GI-NEXT:    ret
+  %add = add nsw <4 x i32> %a, splat(i32 103)
+  %cmp.i = icmp slt <4 x i32> %add, zeroinitializer
+  %sub.i = sub <4 x i32> splat(i32 -103), %a
+  %cond.i = select <4 x i1> %cmp.i, <4 x i32> %sub.i, <4 x i32> %add
+  ret <4 x i32> %cond.i
+}
+
+define <4 x i32> @uabd_i32_select_const_rhs_add(<4 x i32> %b) {
+; CHECK-SD-LABEL: uabd_i32_select_const_rhs_add:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mvni.4s v1, #102
+; CHECK-SD-NEXT:    sabd.4s v0, v0, v1
+; CHECK-SD-NEXT:    neg.4s v0, v0
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: uabd_i32_select_const_rhs_add:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    movi.4s v1, #103
+; CHECK-GI-NEXT:    mvni.4s v2, #102
+; CHECK-GI-NEXT:    add.4s v1, v0, v1
+; CHECK-GI-NEXT:    sub.4s v0, v2, v0
+; CHECK-GI-NEXT:    cmgt.4s v3, v1, #0
+; CHECK-GI-NEXT:    bif.16b v0, v1, v3
+; CHECK-GI-NEXT:    ret
+  %add = add nsw <4 x i32> %b, splat(i32 103)
+  %cmp.i = icmp slt <4 x i32> zeroinitializer, %add
+  %sub.i = sub <4 x i32> splat(i32 -103), %b
+  %cond.i = select <4 x i1> %cmp.i, <4 x i32> %sub.i, <4 x i32> %add
+  ret <4 x i32> %cond.i
+}