[llvm] [LoopInterchange] Update tests generated by UTC (NFC) (PR #181804)
Ryotaro Kasuga via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 17 03:32:56 PST 2026
https://github.com/kasuga-fj created https://github.com/llvm/llvm-project/pull/181804
Update the LoopInterchange tests that use UTC to generate assertions, in order to avoid irrelevant changes during other developments. Most of the changes are simply the result of re-running UTC, but this patch also includes a few additional minor adjustments by hand:
- Rename IR value names to suppress warnings by UTC.
- Delete `NOTE: Assertions have been ...` from the test file that actually doesn't use UTC.
- Delete unnecessary `-pass-remarks-missed=...`.
- Add a store instruction for an unused GEP result, which could otherwise affect other developments.
>From 282a9bced538fd859155ce32e000e1e0ee939843 Mon Sep 17 00:00:00 2001
From: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: Tue, 17 Feb 2026 11:16:59 +0000
Subject: [PATCH] [LoopInterchange] Update tests generated by UTC (NFC)
---
.../LoopInterchange/interchangeable.ll | 12 +--
.../LoopInterchange/lcssa-preheader.ll | 97 +++++++++++++++----
.../LoopInterchange/phi-ordering.ll | 2 +-
.../pr43176-move-to-new-latch.ll | 1 -
.../pr45743-move-from-inner-preheader.ll | 10 +-
.../LoopInterchange/reduction2mem.ll | 4 +-
.../update-condbranch-duplicate-successors.ll | 8 +-
7 files changed, 96 insertions(+), 38 deletions(-)
diff --git a/llvm/test/Transforms/LoopInterchange/interchangeable.ll b/llvm/test/Transforms/LoopInterchange/interchangeable.ll
index 66e59cc1f0c75..72a436a596f62 100644
--- a/llvm/test/Transforms/LoopInterchange/interchangeable.ll
+++ b/llvm/test/Transforms/LoopInterchange/interchangeable.ll
@@ -27,9 +27,9 @@ define void @interchange_01(i64 %k, i64 %N) {
; CHECK-NEXT: br label [[FOR1_HEADER_PREHEADER]]
; CHECK: for2.split1:
; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x [100 x i64]], ptr @A, i64 0, i64 [[J]], i64 [[J23]]
-; CHECK-NEXT: [[LV:%.*]] = load i64, ptr [[ARRAYIDX5]]
+; CHECK-NEXT: [[LV:%.*]] = load i64, ptr [[ARRAYIDX5]], align 8
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[LV]], [[K:%.*]]
-; CHECK-NEXT: store i64 [[ADD]], ptr [[ARRAYIDX5]]
+; CHECK-NEXT: store i64 [[ADD]], ptr [[ARRAYIDX5]], align 8
; CHECK-NEXT: [[J_NEXT:%.*]] = add nuw nsw i64 [[J]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[J]], 99
; CHECK-NEXT: br label [[FOR1_INC10]]
@@ -90,9 +90,9 @@ define void @interchange_02(i64 %k) {
; CHECK-NEXT: br label [[FOR1_HEADER_PREHEADER]]
; CHECK: for3.split1:
; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x [100 x i64]], ptr @A, i64 0, i64 [[J]], i64 [[J19]]
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX5]]
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX5]], align 8
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[K:%.*]]
-; CHECK-NEXT: store i64 [[ADD]], ptr [[ARRAYIDX5]]
+; CHECK-NEXT: store i64 [[ADD]], ptr [[ARRAYIDX5]], align 8
; CHECK-NEXT: [[J_NEXT:%.*]] = add nsw i64 [[J]], -1
; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[J]], 0
; CHECK-NEXT: br label [[FOR1_INC10]]
@@ -160,9 +160,9 @@ define void @interchange_10() {
; CHECK: for2.split1:
; CHECK-NEXT: [[J_NEXT:%.*]] = add nuw nsw i64 [[J]], 1
; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x [100 x i64]], ptr @A, i64 0, i64 [[J]], i64 [[J23]]
-; CHECK-NEXT: store i64 [[J]], ptr [[ARRAYIDX5]]
+; CHECK-NEXT: store i64 [[J]], ptr [[ARRAYIDX5]], align 8
; CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [100 x [100 x i64]], ptr @A, i64 0, i64 [[J]], i64 [[J_NEXT24]]
-; CHECK-NEXT: store i64 [[J23]], ptr [[ARRAYIDX10]]
+; CHECK-NEXT: store i64 [[J23]], ptr [[ARRAYIDX10]], align 8
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[J]], 99
; CHECK-NEXT: br label [[FOR1_INC10]]
; CHECK: for2.split:
diff --git a/llvm/test/Transforms/LoopInterchange/lcssa-preheader.ll b/llvm/test/Transforms/LoopInterchange/lcssa-preheader.ll
index 16c2978a97ba9..ba03fd6ff5880 100644
--- a/llvm/test/Transforms/LoopInterchange/lcssa-preheader.ll
+++ b/llvm/test/Transforms/LoopInterchange/lcssa-preheader.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=loop-interchange -cache-line-size=64 -pass-remarks-missed='loop-interchange' -verify-loop-lcssa -S | FileCheck %s
-; RUN: opt < %s -passes=loop-interchange -cache-line-size=64 -da-disable-delinearization-checks -pass-remarks-missed='loop-interchange' -verify-loop-lcssa -S | FileCheck -check-prefix=CHECK-DELIN %s
+; RUN: opt < %s -passes=loop-interchange -cache-line-size=64 -verify-loop-lcssa -S | FileCheck %s
+; RUN: opt < %s -passes=loop-interchange -cache-line-size=64 -da-disable-delinearization-checks -verify-loop-lcssa -S | FileCheck -check-prefix=CHECK-DELIN %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@@ -16,6 +16,42 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
;; This loop can be interchanged with -da-disable-delinearization-checks, otherwise it cannot
;; be interchanged due to dependence.
define void @lcssa_08(i32 %n, i32 %m) {;
+; CHECK-LABEL: @lcssa_08(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TEMP:%.*]] = alloca [16 x [16 x i32]], align 4
+; CHECK-NEXT: [[RES:%.*]] = alloca [16 x [16 x i32]], align 4
+; CHECK-NEXT: [[CMP24:%.*]] = icmp sgt i32 [[N:%.*]], 0
+; CHECK-NEXT: br i1 [[CMP24]], label [[OUTER_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]]
+; CHECK: outer.preheader:
+; CHECK-NEXT: [[WIDE_TRIP_COUNT29:%.*]] = zext i32 [[N]] to i64
+; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
+; CHECK: outer.header:
+; CHECK-NEXT: [[INDVARS_IV27:%.*]] = phi i64 [ 0, [[OUTER_PREHEADER]] ], [ [[INDVARS_IV_NEXT28:%.*]], [[OUTER_LATCH:%.*]] ]
+; CHECK-NEXT: [[CMP222:%.*]] = icmp sgt i32 [[M:%.*]], 0
+; CHECK-NEXT: br i1 [[CMP222]], label [[INNER_PREHEADER:%.*]], label [[OUTER_LATCH]]
+; CHECK: inner.preheader:
+; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[M]] to i64
+; CHECK-NEXT: br label [[INNER_FOR_BODY:%.*]]
+; CHECK: inner.for.body:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[INNER_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[INNER_FOR_BODY]] ]
+; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [16 x [16 x i32]], ptr [[TEMP]], i64 0, i64 [[INDVARS_IV]], i64 [[INDVARS_IV27]]
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX6]], align 4
+; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [16 x [16 x i32]], ptr [[RES]], i64 0, i64 [[INDVARS_IV]], i64 [[INDVARS_IV27]]
+; CHECK-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX8]], align 4
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[INNER_FOR_BODY]], label [[INNER_CRIT_EDGE:%.*]]
+; CHECK: inner.crit_edge:
+; CHECK-NEXT: br label [[OUTER_LATCH]]
+; CHECK: outer.latch:
+; CHECK-NEXT: [[INDVARS_IV_NEXT28]] = add nuw nsw i64 [[INDVARS_IV27]], 1
+; CHECK-NEXT: [[EXITCOND30:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT28]], [[WIDE_TRIP_COUNT29]]
+; CHECK-NEXT: br i1 [[EXITCOND30]], label [[OUTER_HEADER]], label [[OUTER_CRIT_EDGE:%.*]]
+; CHECK: outer.crit_edge:
+; CHECK-NEXT: br label [[FOR_COND_CLEANUP]]
+; CHECK: for.cond.cleanup:
+; CHECK-NEXT: ret void
+;
; CHECK-DELIN-LABEL: @lcssa_08(
; CHECK-DELIN-NEXT: entry:
; CHECK-DELIN-NEXT: [[TEMP:%.*]] = alloca [16 x [16 x i32]], align 4
@@ -115,35 +151,57 @@ for.cond.cleanup: ; preds = %outer.crit_edge, %e
define void @test2(i32 %N) {
; CHECK-LABEL: @test2(
; CHECK-NEXT: bb:
-; CHECK-NEXT: br label [[INNER_PREHEADER:%.*]]
-; CHECK: outer.header.preheader:
; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
; CHECK: outer.header:
-; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ], [ 0, [[OUTER_HEADER_PREHEADER:%.*]] ]
+; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, [[BB:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[EXIT:%.*]] ]
; CHECK-NEXT: [[N_EXT:%.*]] = sext i32 [[N:%.*]] to i64
-; CHECK-NEXT: br label [[INNER_SPLIT1:%.*]]
-; CHECK: inner.preheader:
; CHECK-NEXT: br label [[INNER:%.*]]
; CHECK: inner:
-; CHECK-NEXT: [[INNER_IV:%.*]] = phi i64 [ [[TMP0:%.*]], [[INNER_SPLIT:%.*]] ], [ 0, [[INNER_PREHEADER]] ]
-; CHECK-NEXT: br label [[OUTER_HEADER_PREHEADER]]
-; CHECK: inner.split1:
+; CHECK-NEXT: [[INNER_IV:%.*]] = phi i64 [ 0, [[OUTER_HEADER]] ], [ [[TMP0:%.*]], [[INNER]] ]
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x [4 x [2 x i16]]], ptr @global, i64 0, i64 [[INNER_IV]], i64 [[OUTER_IV]], i64 0
-; CHECK-NEXT: [[INNER_IV_NEXT:%.*]] = add nsw i64 [[INNER_IV]], 1
-; CHECK-NEXT: [[C_1:%.*]] = icmp ne i64 [[INNER_IV_NEXT]], [[N_EXT]]
-; CHECK-NEXT: br label [[OUTER_LATCH]]
-; CHECK: inner.split:
-; CHECK-NEXT: [[N_EXT_LCSSA:%.*]] = phi i64 [ [[N_EXT]], [[OUTER_LATCH]] ]
+; CHECK-NEXT: store i16 0, ptr [[TMP8]], align 2
; CHECK-NEXT: [[TMP0]] = add nsw i64 [[INNER_IV]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[TMP0]], [[N_EXT_LCSSA]]
-; CHECK-NEXT: br i1 [[TMP1]], label [[INNER]], label [[EXIT:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[TMP0]], [[N_EXT]]
+; CHECK-NEXT: br i1 [[TMP1]], label [[INNER]], label [[EXIT]]
; CHECK: outer.latch:
; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nsw i64 [[OUTER_IV]], 1
; CHECK-NEXT: [[C_2:%.*]] = icmp ne i64 [[OUTER_IV]], [[N_EXT]]
-; CHECK-NEXT: br i1 [[C_2]], label [[OUTER_HEADER]], label [[INNER_SPLIT]]
+; CHECK-NEXT: br i1 [[C_2]], label [[OUTER_HEADER]], label [[INNER_SPLIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
+; CHECK-DELIN-LABEL: @test2(
+; CHECK-DELIN-NEXT: bb:
+; CHECK-DELIN-NEXT: br label [[INNER_PREHEADER:%.*]]
+; CHECK-DELIN: outer.header.preheader:
+; CHECK-DELIN-NEXT: br label [[OUTER_HEADER:%.*]]
+; CHECK-DELIN: outer.header:
+; CHECK-DELIN-NEXT: [[OUTER_IV:%.*]] = phi i64 [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ], [ 0, [[OUTER_HEADER_PREHEADER:%.*]] ]
+; CHECK-DELIN-NEXT: [[N_EXT:%.*]] = sext i32 [[N:%.*]] to i64
+; CHECK-DELIN-NEXT: br label [[INNER_SPLIT1:%.*]]
+; CHECK-DELIN: inner.preheader:
+; CHECK-DELIN-NEXT: br label [[INNER:%.*]]
+; CHECK-DELIN: inner:
+; CHECK-DELIN-NEXT: [[INNER_IV:%.*]] = phi i64 [ [[TMP0:%.*]], [[INNER_SPLIT:%.*]] ], [ 0, [[INNER_PREHEADER]] ]
+; CHECK-DELIN-NEXT: br label [[OUTER_HEADER_PREHEADER]]
+; CHECK-DELIN: inner.split1:
+; CHECK-DELIN-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x [4 x [2 x i16]]], ptr @global, i64 0, i64 [[INNER_IV]], i64 [[OUTER_IV]], i64 0
+; CHECK-DELIN-NEXT: store i16 0, ptr [[TMP8]], align 2
+; CHECK-DELIN-NEXT: [[INNER_IV_NEXT:%.*]] = add nsw i64 [[INNER_IV]], 1
+; CHECK-DELIN-NEXT: [[C_1:%.*]] = icmp ne i64 [[INNER_IV_NEXT]], [[N_EXT]]
+; CHECK-DELIN-NEXT: br label [[OUTER_LATCH]]
+; CHECK-DELIN: inner.split:
+; CHECK-DELIN-NEXT: [[N_EXT_LCSSA:%.*]] = phi i64 [ [[N_EXT]], [[OUTER_LATCH]] ]
+; CHECK-DELIN-NEXT: [[TMP0]] = add nsw i64 [[INNER_IV]], 1
+; CHECK-DELIN-NEXT: [[TMP1:%.*]] = icmp ne i64 [[TMP0]], [[N_EXT_LCSSA]]
+; CHECK-DELIN-NEXT: br i1 [[TMP1]], label [[INNER]], label [[EXIT:%.*]]
+; CHECK-DELIN: outer.latch:
+; CHECK-DELIN-NEXT: [[OUTER_IV_NEXT]] = add nsw i64 [[OUTER_IV]], 1
+; CHECK-DELIN-NEXT: [[C_2:%.*]] = icmp ne i64 [[OUTER_IV]], [[N_EXT]]
+; CHECK-DELIN-NEXT: br i1 [[C_2]], label [[OUTER_HEADER]], label [[INNER_SPLIT]]
+; CHECK-DELIN: exit:
+; CHECK-DELIN-NEXT: ret void
+;
bb:
br label %outer.header
@@ -154,7 +212,8 @@ outer.header: ; preds = %bb11, %bb2
inner: ; preds = %bb6, %bb4
%inner.iv = phi i64 [ 0, %outer.header ], [ %inner.iv.next, %inner ]
- %tmp8 = getelementptr inbounds [4 x [4 x [2 x i16]]], ptr @global, i64 0, i64 %inner.iv, i64 %outer.iv, i64 0
+ %gep = getelementptr inbounds [4 x [4 x [2 x i16]]], ptr @global, i64 0, i64 %inner.iv, i64 %outer.iv, i64 0
+ store i16 0, ptr %gep
%inner.iv.next = add nsw i64 %inner.iv, 1
%c.1 = icmp ne i64 %inner.iv.next, %N.ext
br i1 %c.1, label %inner, label %outer.latch
diff --git a/llvm/test/Transforms/LoopInterchange/phi-ordering.ll b/llvm/test/Transforms/LoopInterchange/phi-ordering.ll
index 74709f2eb7575..cb5b8db412e24 100644
--- a/llvm/test/Transforms/LoopInterchange/phi-ordering.ll
+++ b/llvm/test/Transforms/LoopInterchange/phi-ordering.ll
@@ -33,7 +33,7 @@ define void @test(i32 %T, ptr noalias nocapture %C, ptr noalias nocapture readon
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [90 x [90 x i16]], ptr [[A:%.*]], i32 [[ADD]], i32 [[I]], i32 [[J]]
; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
; CHECK-NEXT: [[ADD15:%.*]] = add nsw i16 [[TMP0]], 1
-; CHECK-NEXT: store i16 [[ADD15]], ptr [[ARRAYIDX]]
+; CHECK-NEXT: store i16 [[ADD15]], ptr [[ARRAYIDX]], align 2
; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i32 [[K]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], 90
; CHECK-NEXT: br label [[FOR2_INC16]]
diff --git a/llvm/test/Transforms/LoopInterchange/pr43176-move-to-new-latch.ll b/llvm/test/Transforms/LoopInterchange/pr43176-move-to-new-latch.ll
index f02ee1a0ced19..69ef1e8ff7b95 100644
--- a/llvm/test/Transforms/LoopInterchange/pr43176-move-to-new-latch.ll
+++ b/llvm/test/Transforms/LoopInterchange/pr43176-move-to-new-latch.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=loop-interchange -cache-line-size=64 -pass-remarks-missed='loop-interchange' -pass-remarks-output=%t -S
; RUN: FileCheck --input-file=%t %s
diff --git a/llvm/test/Transforms/LoopInterchange/pr45743-move-from-inner-preheader.ll b/llvm/test/Transforms/LoopInterchange/pr45743-move-from-inner-preheader.ll
index e7c7bf2a71819..8f9e3e7a16bc3 100644
--- a/llvm/test/Transforms/LoopInterchange/pr45743-move-from-inner-preheader.ll
+++ b/llvm/test/Transforms/LoopInterchange/pr45743-move-from-inner-preheader.ll
@@ -3,7 +3,7 @@
@global = external local_unnamed_addr global [400 x [400 x i32]], align 16
-; We need to move %tmp4 from the inner loop pre header to the outer loop header
+; We need to move %mul from the inner loop pre header to the outer loop header
; before interchanging.
define void @test1() local_unnamed_addr #0 {
; CHECK-LABEL: @test1(
@@ -50,13 +50,13 @@ outer.header: ; preds = %bb11, %bb
br label %inner.ph
inner.ph: ; preds = %bb1
- %tmp4 = add nsw i64 %outer.iv, 9
+ %mul = add nsw i64 %outer.iv, 9
br label %inner
inner: ; preds = %bb5, %bb3
%inner.iv = phi i64 [ 0, %inner.ph ], [ %inner.iv.next, %inner ]
%inner.red = phi i32 [ %outer.red, %inner.ph ], [ %red.next, %inner ]
- %ptr = getelementptr inbounds [400 x [400 x i32]], ptr @global, i64 0, i64 %inner.iv, i64 %tmp4
+ %ptr = getelementptr inbounds [400 x [400 x i32]], ptr @global, i64 0, i64 %inner.iv, i64 %mul
store i32 0, ptr %ptr
%red.next = or i32 %inner.red, 20
%inner.iv.next = add nsw i64 %inner.iv, 1
@@ -116,14 +116,14 @@ outer.header: ; preds = %bb11, %bb
br label %inner.ph
inner.ph: ; preds = %bb1
- %tmp4 = add nsw i64 %outer.iv, 9
+ %mul = add nsw i64 %outer.iv, 9
call void @side_effect()
br label %inner
inner: ; preds = %bb5, %bb3
%inner.iv = phi i64 [ 0, %inner.ph ], [ %inner.iv.next, %inner ]
%inner.red = phi i32 [ %outer.red, %inner.ph ], [ %red.next, %inner ]
- %ptr = getelementptr inbounds [400 x [400 x i32]], ptr @global, i64 0, i64 %inner.iv, i64 %tmp4
+ %ptr = getelementptr inbounds [400 x [400 x i32]], ptr @global, i64 0, i64 %inner.iv, i64 %mul
store i32 0, ptr %ptr
%red.next = or i32 %inner.red, 20
%inner.iv.next = add nsw i64 %inner.iv, 1
diff --git a/llvm/test/Transforms/LoopInterchange/reduction2mem.ll b/llvm/test/Transforms/LoopInterchange/reduction2mem.ll
index de05b5ce4e5de..82b20361c8726 100644
--- a/llvm/test/Transforms/LoopInterchange/reduction2mem.ll
+++ b/llvm/test/Transforms/LoopInterchange/reduction2mem.ll
@@ -27,7 +27,7 @@ define void @func(ptr noalias readonly %a, ptr noalias readonly %b, ptr noalias
; CHECK-NEXT: br label %[[INNERLOOP:.*]]
; CHECK: [[INNERLOOP]]:
; CHECK-NEXT: [[INDEX_J:%.*]] = phi i64 [ [[J_NEXT:%.*]], %[[INNERLOOP_SPLIT:.*]] ], [ 0, %[[INNERLOOP_PREHEADER]] ]
-; CHECK-NEXT: [[DEAD_REDUCTION:%.*]] = phi double [ [[ADD_LCSSA:%.*]], %[[INNERLOOP_SPLIT]] ], [ 0.000000e+00, %[[INNERLOOP_PREHEADER]] ]
+; CHECK-NEXT: [[REDUCTION:%.*]] = phi double [ [[ADD_LCSSA:%.*]], %[[INNERLOOP_SPLIT]] ], [ 0.000000e+00, %[[INNERLOOP_PREHEADER]] ]
; CHECK-NEXT: [[FIRSTITER:%.*]] = phi i1 [ false, %[[INNERLOOP_SPLIT]] ], [ true, %[[INNERLOOP_PREHEADER]] ]
; CHECK-NEXT: br label %[[OUTERLOOPHEADER_PREHEADER]]
; CHECK: [[INNERLOOP_SPLIT1]]:
@@ -45,7 +45,7 @@ define void @func(ptr noalias readonly %a, ptr noalias readonly %b, ptr noalias
; CHECK-NEXT: br label %[[OUTERLOOP_LATCH]]
; CHECK: [[INNERLOOP_SPLIT]]:
; CHECK-NEXT: [[ADD_LCSSA]] = phi double [ [[ADD]], %[[OUTERLOOP_LATCH]] ]
-; CHECK-NEXT: [[DEAD_LCSSA:%.*]] = phi double [ [[ADD]], %[[OUTERLOOP_LATCH]] ]
+; CHECK-NEXT: [[LCSSA:%.*]] = phi double [ [[ADD]], %[[OUTERLOOP_LATCH]] ]
; CHECK-NEXT: [[J_NEXT]] = add nuw nsw i64 [[INDEX_J]], 1
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i64 [[J_NEXT]], [[N]]
; CHECK-NEXT: br i1 [[CMP1]], label %[[EXIT_LOOPEXIT:.*]], label %[[INNERLOOP]]
diff --git a/llvm/test/Transforms/LoopInterchange/update-condbranch-duplicate-successors.ll b/llvm/test/Transforms/LoopInterchange/update-condbranch-duplicate-successors.ll
index 7c393721c1a5d..d2d0e844ebcb6 100644
--- a/llvm/test/Transforms/LoopInterchange/update-condbranch-duplicate-successors.ll
+++ b/llvm/test/Transforms/LoopInterchange/update-condbranch-duplicate-successors.ll
@@ -23,9 +23,9 @@ define void @foo(i1 %cmp) {
; CHECK-NEXT: br label [[BB1]]
; CHECK: inner.header.split1:
; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds [1000 x [1000 x i32]], ptr @global, i64 0, i64 [[INNER_IV]], i64 [[OUTER_IV]]
-; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[PTR]]
+; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[PTR]], align 4
; CHECK-NEXT: [[V:%.*]] = mul i32 [[LV]], 100
-; CHECK-NEXT: store i32 [[V]], ptr [[PTR]]
+; CHECK-NEXT: store i32 [[V]], ptr [[PTR]], align 4
; CHECK-NEXT: [[INNER_IV_NEXT:%.*]] = add nsw i64 [[INNER_IV]], 1
; CHECK-NEXT: [[COND1:%.*]] = icmp eq i64 [[INNER_IV_NEXT]], 1000
; CHECK-NEXT: br label [[OUTER_LATCH]]
@@ -93,9 +93,9 @@ define void @foo1(i1 %cmp) {
; CHECK-NEXT: br label [[OUTER_HEADER_PREHEADER]]
; CHECK: inner.header.split1:
; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds [1000 x [1000 x i32]], ptr @global, i64 0, i64 [[INNER_IV]], i64 [[OUTER_IV]]
-; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[PTR]]
+; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[PTR]], align 4
; CHECK-NEXT: [[V:%.*]] = mul i32 [[LV]], 100
-; CHECK-NEXT: store i32 [[V]], ptr [[PTR]]
+; CHECK-NEXT: store i32 [[V]], ptr [[PTR]], align 4
; CHECK-NEXT: [[INNER_IV_NEXT:%.*]] = add nsw i64 [[INNER_IV]], 1
; CHECK-NEXT: [[COND1:%.*]] = icmp eq i64 [[INNER_IV_NEXT]], 1000
; CHECK-NEXT: br label [[OUTER_LATCH]]
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