[llvm] [AArch64] Prefer SVE2 for fixed-length i64 [S|U][MIN|MAX] reductions (PR #181161)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 79ed46739..2abc7007f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17360,15 +17360,16 @@ SDValue AArch64TargetLowering::LowerVECREDUCE(SDValue Op,
                       (Op.getOpcode() != ISD::VECREDUCE_ADD &&
                        SrcVT.getVectorElementType() == MVT::i64);
 
-  bool UsesSVEForFixedLengthVT =  useSVEForFixedLengthVectorVT(
-          SrcVT, OverrideNEON && Subtarget->useSVEForFixedLengthVectors());
+  bool UsesSVEForFixedLengthVT = useSVEForFixedLengthVectorVT(
+      SrcVT, OverrideNEON && Subtarget->useSVEForFixedLengthVectors());
 
   // Always lower try to lower v2i64 pairwise operations (as NEON does not
   // natively support reductions on these types). Try lowering any v2<ty> vector
   // to pairwise operations when using SVE for fixed-length VTs, as the pairwise
   // operations are likely to be cheaper than a full reduction.
   bool TryPairwiseOps = SrcVT == MVT::v2i64 || (UsesSVEForFixedLengthVT &&
-    SrcVT.getVectorElementCount() ==  ElementCount::getFixed(2));
+                                                SrcVT.getVectorElementCount() ==
+                                                    ElementCount::getFixed(2));
 
   // Attempt to lower v2<ty> reductions to SVE2 pairwise operations.
   auto PairwiseIID = getPairwiseOpForReduction(Op->getOpcode());

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https://github.com/llvm/llvm-project/pull/181161