[llvm] [AArch64][GlobalISel] Use GPR for illegal fconstants and extend < 32 bit GPR constants to 32 bits (PR #178692)

[Ryan Cowan via llvm-commits]

================
@@ -1,60 +1,122 @@
-; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-apple-darwin -global-isel | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck --check-prefixes=CHECK,CHECK-SD %s
+; RUN: llc < %s -mtriple=arm64-apple-darwin -global-isel | FileCheck --check-prefixes=CHECK,CHECK-GI %s
 
-; CHECK: literal8
-; CHECK: .quad  0x400921fb54442d18
 define double @foo() optsize {
-; CHECK: _foo:
-; CHECK: adrp x[[REG:[0-9]+]], lCPI0_0 at PAGE
-; CHECK: ldr  d0, [x[[REG]], lCPI0_0 at PAGEOFF]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: foo:
+; CHECK-SD:       ; %bb.0:
+; CHECK-SD-NEXT:  Lloh0:
+; CHECK-SD-NEXT:    adrp x8, lCPI0_0 at PAGE
+; CHECK-SD-NEXT:  Lloh1:
+; CHECK-SD-NEXT:    ldr d0, [x8, lCPI0_0 at PAGEOFF]
+; CHECK-SD-NEXT:    ret
+; CHECK-SD-NEXT:    .loh AdrpLdr Lloh0, Lloh1
+;
+; CHECK-GI-LABEL: foo:
+; CHECK-GI:       ; %bb.0:
+; CHECK-GI-NEXT:    mov x8, #11544 ; =0x2d18
+; CHECK-GI-NEXT:    movk x8, #21572, lsl #16
+; CHECK-GI-NEXT:    movk x8, #8699, lsl #32
+; CHECK-GI-NEXT:    movk x8, #16393, lsl #48
+; CHECK-GI-NEXT:    fmov d0, x8
+; CHECK-GI-NEXT:    ret
----------------
HolyMolyCowMan wrote:

Yes it is. I'm not sure if this is better but a comment in `AArch64TargetLowering::isFPImmLegal` suggests it is a better sequence of instructions:
```
    // The cost is actually exactly the same for mov+fmov vs. adrp+ldr;
    // however the mov+fmov sequence is always better because of the reduced
    // cache pressure. The timings are still the same if you consider
    // movw+movk+fmov vs. adrp+ldr (it's one instruction longer, but the
    // movw+movk is fused). So we limit up to 4 instructions at most.
```

https://github.com/llvm/llvm-project/pull/178692