[llvm] [X86][APX] Fix assembly printing for NF+ND shift-by-1 instructions (PR #181565)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 17 02:39:55 PST 2026
https://github.com/moleium updated https://github.com/llvm/llvm-project/pull/181565
>From 4e8367df204911bf2261e9e3d992ba84c548b0f9 Mon Sep 17 00:00:00 2001
From: moleium <molenoch at protonmail.com>
Date: Sun, 15 Feb 2026 22:09:43 +0300
Subject: [PATCH 1/5] [X86][APX] Fix assembly printing for NF+ND shift-by-1
instructions
---
.../X86/MCTargetDesc/X86ATTInstPrinter.cpp | 86 +++++++++++++++++++
.../X86/MCTargetDesc/X86ATTInstPrinter.h | 2 +
llvm/lib/Target/X86/X86InstrShiftRotate.td | 4 +-
3 files changed, 90 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
index 564636959f00f..d40c803307be0 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
@@ -402,6 +402,92 @@ bool X86ATTInstPrinter::printVecCompareInstr(const MCInst *MI,
return false;
}
+bool X86ATTInstPrinter::printShiftBy1NFNDInstr(const MCInst *MI,
+ uint64_t Address,
+ raw_ostream &OS) {
+ // Emit explicit $1 for shift-by-1 NF+ND to match binutils behavior.
+ const char *Mnemonic = nullptr;
+ const char *Suffix = nullptr;
+
+ switch (MI->getOpcode()) {
+ default:
+ return false;
+
+ case X86::SHL16r1_NF_ND:
+ Mnemonic = "shl";
+ Suffix = "w";
+ break;
+ case X86::SHL32r1_NF_ND:
+ Mnemonic = "shl";
+ Suffix = "l";
+ break;
+ case X86::SHL64r1_NF_ND:
+ Mnemonic = "shl";
+ Suffix = "q";
+ break;
+
+ case X86::SHR16r1_NF_ND:
+ Mnemonic = "shr";
+ Suffix = "w";
+ break;
+ case X86::SHR32r1_NF_ND:
+ Mnemonic = "shr";
+ Suffix = "l";
+ break;
+ case X86::SHR64r1_NF_ND:
+ Mnemonic = "shr";
+ Suffix = "q";
+ break;
+
+ case X86::SAR16r1_NF_ND:
+ Mnemonic = "sar";
+ Suffix = "w";
+ break;
+ case X86::SAR32r1_NF_ND:
+ Mnemonic = "sar";
+ Suffix = "l";
+ break;
+ case X86::SAR64r1_NF_ND:
+ Mnemonic = "sar";
+ Suffix = "q";
+ break;
+
+ case X86::ROL16r1_NF_ND:
+ Mnemonic = "rol";
+ Suffix = "w";
+ break;
+ case X86::ROL32r1_NF_ND:
+ Mnemonic = "rol";
+ Suffix = "l";
+ break;
+ case X86::ROL64r1_NF_ND:
+ Mnemonic = "rol";
+ Suffix = "q";
+ break;
+
+ case X86::ROR16r1_NF_ND:
+ Mnemonic = "ror";
+ Suffix = "w";
+ break;
+ case X86::ROR32r1_NF_ND:
+ Mnemonic = "ror";
+ Suffix = "l";
+ break;
+ case X86::ROR64r1_NF_ND:
+ Mnemonic = "ror";
+ Suffix = "q";
+ break;
+ }
+
+ // NDD operands are stored as (dst, src).
+ OS << '\t' << Mnemonic << Suffix << "\t$1, ";
+ printOperand(MI, 1, OS);
+ OS << ", ";
+ printOperand(MI, 0, OS);
+
+ return true;
+}
+
void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h
index 1452622ebcea8..9179f0704cc8f 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h
@@ -28,6 +28,8 @@ class X86ATTInstPrinter final : public X86InstPrinterCommon {
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &OS) override;
bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
+ bool printShiftBy1NFNDInstr(const MCInst *MI, uint64_t Address,
+ raw_ostream &OS);
// Autogenerated by tblgen, returns true if we successfully printed an
// alias.
diff --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td b/llvm/lib/Target/X86/X86InstrShiftRotate.td
index 2a5488847e648..9775e23a929d7 100644
--- a/llvm/lib/Target/X86/X86InstrShiftRotate.td
+++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td
@@ -70,7 +70,7 @@ multiclass ShiftRotate<string m, Format RegMRM, Format MemMRM, SDPatternOperator
// GNU binutils distinguish them by adding an explicit $1 to asm string of 8r1_ND. But we haven't support
// constant immediate in asm string for X86 in TD. So we add DisassembleOnly for 8r1_ND for the time being.
let Predicates = [In64BitMode] in {
- def 8r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi8, null_frag, 1>, DisassembleOnly;
+ def 8r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi8, null_frag, 1>;
def 16r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi16, null_frag, 1>, PD;
def 32r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi32, null_frag, 1>;
def 64r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi64, null_frag, 1>;
@@ -181,7 +181,7 @@ multiclass ShiftRotate_NF<string m, Format RegMRM, Format MemMRM, SchedReadWrite
def 32r1_NF : UnaryOpR_R<0xD1, RegMRM, m, Xi32>, NF;
def 64r1_NF : UnaryOpR_R<0xD1, RegMRM, m, Xi64>, NF;
- def 8r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi8, null_frag, 1>, EVEX_NF, DisassembleOnly;
+ def 8r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi8, null_frag, 1>, EVEX_NF;
def 16r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi16, null_frag, 1>, EVEX_NF, PD;
def 32r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi32, null_frag, 1>, EVEX_NF;
def 64r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi64, null_frag, 1>, EVEX_NF;
>From a1410cc5f72d25a44e17a81165c6f91f48d89258 Mon Sep 17 00:00:00 2001
From: moleium <molenoch at protonmail.com>
Date: Tue, 17 Feb 2026 12:32:59 +0300
Subject: [PATCH 2/5] Add 8 bit support and use char for suffix
---
.../X86/MCTargetDesc/X86ATTInstPrinter.cpp | 56 +++++++++++++------
1 file changed, 39 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
index d40c803307be0..c29a40bb7119d 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
@@ -85,7 +85,9 @@ void X86ATTInstPrinter::printInst(const MCInst *MI, uint64_t Address,
OS << "\tdata32";
}
// Try to print any aliases first.
- else if (!printAliasInstr(MI, Address, OS) && !printVecCompareInstr(MI, OS))
+ else if (!printShiftBy1NFNDInstr(MI, Address, OS) &&
+ !printAliasInstr(MI, Address, OS) &&
+ !printVecCompareInstr(MI, OS))
printInstruction(MI, Address, OS);
// Next always print the annotation.
@@ -407,75 +409,95 @@ bool X86ATTInstPrinter::printShiftBy1NFNDInstr(const MCInst *MI,
raw_ostream &OS) {
// Emit explicit $1 for shift-by-1 NF+ND to match binutils behavior.
const char *Mnemonic = nullptr;
- const char *Suffix = nullptr;
+ char Suffix = 0;
switch (MI->getOpcode()) {
default:
return false;
+ case X86::SHL8r1_NF_ND:
+ Mnemonic = "shl";
+ Suffix = 'b';
+ break;
case X86::SHL16r1_NF_ND:
Mnemonic = "shl";
- Suffix = "w";
+ Suffix = 'w';
break;
case X86::SHL32r1_NF_ND:
Mnemonic = "shl";
- Suffix = "l";
+ Suffix = 'l';
break;
case X86::SHL64r1_NF_ND:
Mnemonic = "shl";
- Suffix = "q";
+ Suffix = 'q';
break;
+ case X86::SHR8r1_NF_ND:
+ Mnemonic = "shr";
+ Suffix = 'b';
+ break;
case X86::SHR16r1_NF_ND:
Mnemonic = "shr";
- Suffix = "w";
+ Suffix = 'w';
break;
case X86::SHR32r1_NF_ND:
Mnemonic = "shr";
- Suffix = "l";
+ Suffix = 'l';
break;
case X86::SHR64r1_NF_ND:
Mnemonic = "shr";
- Suffix = "q";
+ Suffix = 'q';
break;
+ case X86::SAR8r1_NF_ND:
+ Mnemonic = "sar";
+ Suffix = 'b';
+ break;
case X86::SAR16r1_NF_ND:
Mnemonic = "sar";
- Suffix = "w";
+ Suffix = 'w';
break;
case X86::SAR32r1_NF_ND:
Mnemonic = "sar";
- Suffix = "l";
+ Suffix = 'l';
break;
case X86::SAR64r1_NF_ND:
Mnemonic = "sar";
- Suffix = "q";
+ Suffix = 'q';
break;
+ case X86::ROL8r1_NF_ND:
+ Mnemonic = "rol";
+ Suffix = 'b';
+ break;
case X86::ROL16r1_NF_ND:
Mnemonic = "rol";
- Suffix = "w";
+ Suffix = 'w';
break;
case X86::ROL32r1_NF_ND:
Mnemonic = "rol";
- Suffix = "l";
+ Suffix = 'l';
break;
case X86::ROL64r1_NF_ND:
Mnemonic = "rol";
- Suffix = "q";
+ Suffix = 'q';
break;
+ case X86::ROR8r1_NF_ND:
+ Mnemonic = "ror";
+ Suffix = 'b';
+ break;
case X86::ROR16r1_NF_ND:
Mnemonic = "ror";
- Suffix = "w";
+ Suffix = 'w';
break;
case X86::ROR32r1_NF_ND:
Mnemonic = "ror";
- Suffix = "l";
+ Suffix = 'l';
break;
case X86::ROR64r1_NF_ND:
Mnemonic = "ror";
- Suffix = "q";
+ Suffix = 'q';
break;
}
>From 26e46f65ec57a88a2115e79dfc382616679a973d Mon Sep 17 00:00:00 2001
From: moleium <molenoch at protonmail.com>
Date: Tue, 17 Feb 2026 12:52:47 +0300
Subject: [PATCH 3/5] Add tests for APX shift-by-1 NF+ND instructions
---
llvm/test/MC/X86/apx/shift-one-att.s | 81 ++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
create mode 100644 llvm/test/MC/X86/apx/shift-one-att.s
diff --git a/llvm/test/MC/X86/apx/shift-one-att.s b/llvm/test/MC/X86/apx/shift-one-att.s
new file mode 100644
index 0000000000000..ee5f3b0b7720e
--- /dev/null
+++ b/llvm/test/MC/X86/apx/shift-one-att.s
@@ -0,0 +1,81 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+
+# CHECK: {nf} shlb $1, %cl, %dl
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd0,0xe1]
+{nf} shlb $1, %cl, %dl
+
+# CHECK: {nf} shlw $1, %cx, %dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xe1]
+{nf} shlw $1, %cx, %dx
+
+# CHECK: {nf} shll $1, %ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd1,0xe1]
+{nf} shll $1, %ecx, %edx
+
+# CHECK: {nf} shlq $1, %rcx, %rdx
+# CHECK: encoding: [0x62,0xf4,0xec,0x1c,0xd1,0xe1]
+{nf} shlq $1, %rcx, %rdx
+
+# CHECK: {nf} shrb $1, %cl, %dl
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd0,0xe9]
+{nf} shrb $1, %cl, %dl
+
+# CHECK: {nf} shrw $1, %cx, %dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xe9]
+{nf} shrw $1, %cx, %dx
+
+# CHECK: {nf} shrl $1, %ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd1,0xe9]
+{nf} shrl $1, %ecx, %edx
+
+# CHECK: {nf} shrq $1, %rcx, %rdx
+# CHECK: encoding: [0x62,0xf4,0xec,0x1c,0xd1,0xe9]
+{nf} shrq $1, %rcx, %rdx
+
+# CHECK: {nf} sarb $1, %cl, %dl
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd0,0xf9]
+{nf} sarb $1, %cl, %dl
+
+# CHECK: {nf} sarw $1, %cx, %dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xf9]
+{nf} sarw $1, %cx, %dx
+
+# CHECK: {nf} sarl $1, %ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd1,0xf9]
+{nf} sarl $1, %ecx, %edx
+
+# CHECK: {nf} sarq $1, %rcx, %rdx
+# CHECK: encoding: [0x62,0xf4,0xec,0x1c,0xd1,0xf9]
+{nf} sarq $1, %rcx, %rdx
+
+# CHECK: {nf} rolb $1, %cl, %dl
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd0,0xc1]
+{nf} rolb $1, %cl, %dl
+
+# CHECK: {nf} rolw $1, %cx, %dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xc1]
+{nf} rolw $1, %cx, %dx
+
+# CHECK: {nf} roll $1, %ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd1,0xc1]
+{nf} roll $1, %ecx, %edx
+
+# CHECK: {nf} rolq $1, %rcx, %rdx
+# CHECK: encoding: [0x62,0xf4,0xec,0x1c,0xd1,0xc1]
+{nf} rolq $1, %rcx, %rdx
+
+# CHECK: {nf} rorb $1, %cl, %dl
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd0,0xc9]
+{nf} rorb $1, %cl, %dl
+
+# CHECK: {nf} rorw $1, %cx, %dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xc9]
+{nf} rorw $1, %cx, %dx
+
+# CHECK: {nf} rorl $1, %ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd1,0xc9]
+{nf} rorl $1, %ecx, %edx
+
+# CHECK: {nf} rorq $1, %rcx, %rdx
+# CHECK: encoding: [0x62,0xf4,0xec,0x1c,0xd1,0xc9]
+{nf} rorq $1, %rcx, %rdx
>From 8ae9c4db77232f0b424f2d083ac019c116ed6f72 Mon Sep 17 00:00:00 2001
From: moleium <molenoch at protonmail.com>
Date: Tue, 17 Feb 2026 12:55:24 +0300
Subject: [PATCH 4/5] Fix clang-format
---
llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
index c29a40bb7119d..34c7e46c9b059 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
@@ -86,8 +86,7 @@ void X86ATTInstPrinter::printInst(const MCInst *MI, uint64_t Address,
}
// Try to print any aliases first.
else if (!printShiftBy1NFNDInstr(MI, Address, OS) &&
- !printAliasInstr(MI, Address, OS) &&
- !printVecCompareInstr(MI, OS))
+ !printAliasInstr(MI, Address, OS) && !printVecCompareInstr(MI, OS))
printInstruction(MI, Address, OS);
// Next always print the annotation.
>From a473ccbcfe7c630fcfbe235b9fd93b0ebd790ee0 Mon Sep 17 00:00:00 2001
From: moleium <molenoch at protonmail.com>
Date: Tue, 17 Feb 2026 13:39:36 +0300
Subject: [PATCH 5/5] Update existing APX shift tests to expect explicit
immediate
---
llvm/test/CodeGen/X86/apx/shr.ll | 8 ++++----
llvm/test/MC/Disassembler/X86/apx/rol.txt | 8 ++++----
llvm/test/MC/Disassembler/X86/apx/ror.txt | 8 ++++----
llvm/test/MC/Disassembler/X86/apx/sar.txt | 8 ++++----
llvm/test/MC/Disassembler/X86/apx/shl.txt | 8 ++++----
llvm/test/MC/Disassembler/X86/apx/shr.txt | 8 ++++----
llvm/test/MC/X86/apx/rol-att.s | 12 ++++++------
llvm/test/MC/X86/apx/rol-encopt.s | 8 ++++----
llvm/test/MC/X86/apx/ror-att.s | 12 ++++++------
llvm/test/MC/X86/apx/ror-encopt.s | 8 ++++----
llvm/test/MC/X86/apx/sar-att.s | 12 ++++++------
llvm/test/MC/X86/apx/sar-encopt.s | 8 ++++----
llvm/test/MC/X86/apx/shl-att.s | 12 ++++++------
llvm/test/MC/X86/apx/shl-encopt.s | 8 ++++----
llvm/test/MC/X86/apx/shr-att.s | 12 ++++++------
llvm/test/MC/X86/apx/shr-encopt.s | 8 ++++----
16 files changed, 74 insertions(+), 74 deletions(-)
diff --git a/llvm/test/CodeGen/X86/apx/shr.ll b/llvm/test/CodeGen/X86/apx/shr.ll
index b82000bd950dc..acbd6a66408b9 100644
--- a/llvm/test/CodeGen/X86/apx/shr.ll
+++ b/llvm/test/CodeGen/X86/apx/shr.ll
@@ -303,7 +303,7 @@ define i8 @shr8r1(i8 noundef %a) {
;
; NF-LABEL: shr8r1:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} shrb %dil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xd0,0xef]
+; NF-NEXT: {nf} shrb $1, %dil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xd0,0xef]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%shr = lshr i8 %a, 1
@@ -318,7 +318,7 @@ define i16 @shr16r1(i16 noundef %a) {
;
; NF-LABEL: shr16r1:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} shrw %di, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0xd1,0xef]
+; NF-NEXT: {nf} shrw $1, %di, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0xd1,0xef]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%shr = lshr i16 %a, 1
@@ -333,7 +333,7 @@ define i32 @shr32r1(i32 noundef %a) {
;
; NF-LABEL: shr32r1:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} shrl %edi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xd1,0xef]
+; NF-NEXT: {nf} shrl $1, %edi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xd1,0xef]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%shr = lshr i32 %a, 1
@@ -348,7 +348,7 @@ define i64 @shr64r1(i64 noundef %a) {
;
; NF-LABEL: shr64r1:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} shrq %rdi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0xd1,0xef]
+; NF-NEXT: {nf} shrq $1, %rdi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0xd1,0xef]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%shr = lshr i64 %a, 1
diff --git a/llvm/test/MC/Disassembler/X86/apx/rol.txt b/llvm/test/MC/Disassembler/X86/apx/rol.txt
index bb713d1c88566..92298c36c49a9 100644
--- a/llvm/test/MC/Disassembler/X86/apx/rol.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/rol.txt
@@ -141,7 +141,7 @@
# INTEL: rol bl, bl
0x62,0xf4,0x64,0x18,0xd0,0xc3
-# ATT: {nf} rolb %bl, %bl
+# ATT: {nf} rolb $1, %bl, %bl
# INTEL: {nf} rol bl, bl
0x62,0xf4,0x64,0x1c,0xd0,0xc3
@@ -285,7 +285,7 @@
# INTEL: rol dx, dx
0x62,0xf4,0x6d,0x18,0xd1,0xc2
-# ATT: {nf} rolw %dx, %dx
+# ATT: {nf} rolw $1, %dx, %dx
# INTEL: {nf} rol dx, dx
0x62,0xf4,0x6d,0x1c,0xd1,0xc2
@@ -301,7 +301,7 @@
# INTEL: rol ecx, ecx
0x62,0xf4,0x74,0x18,0xd1,0xc1
-# ATT: {nf} roll %ecx, %ecx
+# ATT: {nf} roll $1, %ecx, %ecx
# INTEL: {nf} rol ecx, ecx
0x62,0xf4,0x74,0x1c,0xd1,0xc1
@@ -317,7 +317,7 @@
# INTEL: rol r9, r9
0x62,0xd4,0xb4,0x18,0xd1,0xc1
-# ATT: {nf} rolq %r9, %r9
+# ATT: {nf} rolq $1, %r9, %r9
# INTEL: {nf} rol r9, r9
0x62,0xd4,0xb4,0x1c,0xd1,0xc1
diff --git a/llvm/test/MC/Disassembler/X86/apx/ror.txt b/llvm/test/MC/Disassembler/X86/apx/ror.txt
index 484a3e143fdac..2a954f82d48a2 100644
--- a/llvm/test/MC/Disassembler/X86/apx/ror.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/ror.txt
@@ -141,7 +141,7 @@
# INTEL: ror bl, bl
0x62,0xf4,0x64,0x18,0xd0,0xcb
-# ATT: {nf} rorb %bl, %bl
+# ATT: {nf} rorb $1, %bl, %bl
# INTEL: {nf} ror bl, bl
0x62,0xf4,0x64,0x1c,0xd0,0xcb
@@ -285,7 +285,7 @@
# INTEL: ror dx, dx
0x62,0xf4,0x6d,0x18,0xd1,0xca
-# ATT: {nf} rorw %dx, %dx
+# ATT: {nf} rorw $1, %dx, %dx
# INTEL: {nf} ror dx, dx
0x62,0xf4,0x6d,0x1c,0xd1,0xca
@@ -301,7 +301,7 @@
# INTEL: ror ecx, ecx
0x62,0xf4,0x74,0x18,0xd1,0xc9
-# ATT: {nf} rorl %ecx, %ecx
+# ATT: {nf} rorl $1, %ecx, %ecx
# INTEL: {nf} ror ecx, ecx
0x62,0xf4,0x74,0x1c,0xd1,0xc9
@@ -317,7 +317,7 @@
# INTEL: ror r9, r9
0x62,0xd4,0xb4,0x18,0xd1,0xc9
-# ATT: {nf} rorq %r9, %r9
+# ATT: {nf} rorq $1, %r9, %r9
# INTEL: {nf} ror r9, r9
0x62,0xd4,0xb4,0x1c,0xd1,0xc9
diff --git a/llvm/test/MC/Disassembler/X86/apx/sar.txt b/llvm/test/MC/Disassembler/X86/apx/sar.txt
index b5e41ee956ccd..fca8b2ccec3ce 100644
--- a/llvm/test/MC/Disassembler/X86/apx/sar.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/sar.txt
@@ -141,7 +141,7 @@
# INTEL: sar bl, bl
0x62,0xf4,0x64,0x18,0xd0,0xfb
-# ATT: {nf} sarb %bl, %bl
+# ATT: {nf} sarb $1, %bl, %bl
# INTEL: {nf} sar bl, bl
0x62,0xf4,0x64,0x1c,0xd0,0xfb
@@ -285,7 +285,7 @@
# INTEL: sar dx, dx
0x62,0xf4,0x6d,0x18,0xd1,0xfa
-# ATT: {nf} sarw %dx, %dx
+# ATT: {nf} sarw $1, %dx, %dx
# INTEL: {nf} sar dx, dx
0x62,0xf4,0x6d,0x1c,0xd1,0xfa
@@ -301,7 +301,7 @@
# INTEL: sar ecx, ecx
0x62,0xf4,0x74,0x18,0xd1,0xf9
-# ATT: {nf} sarl %ecx, %ecx
+# ATT: {nf} sarl $1, %ecx, %ecx
# INTEL: {nf} sar ecx, ecx
0x62,0xf4,0x74,0x1c,0xd1,0xf9
@@ -317,7 +317,7 @@
# INTEL: sar r9, r9
0x62,0xd4,0xb4,0x18,0xd1,0xf9
-# ATT: {nf} sarq %r9, %r9
+# ATT: {nf} sarq $1, %r9, %r9
# INTEL: {nf} sar r9, r9
0x62,0xd4,0xb4,0x1c,0xd1,0xf9
diff --git a/llvm/test/MC/Disassembler/X86/apx/shl.txt b/llvm/test/MC/Disassembler/X86/apx/shl.txt
index 6f0b1b9a2af2e..3f2bb99526361 100644
--- a/llvm/test/MC/Disassembler/X86/apx/shl.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/shl.txt
@@ -141,7 +141,7 @@
# INTEL: shl bl, bl
0x62,0xf4,0x64,0x18,0xd0,0xe3
-# ATT: {nf} shlb %bl, %bl
+# ATT: {nf} shlb $1, %bl, %bl
# INTEL: {nf} shl bl, bl
0x62,0xf4,0x64,0x1c,0xd0,0xe3
@@ -285,7 +285,7 @@
# INTEL: shl dx, dx
0x62,0xf4,0x6d,0x18,0xd1,0xe2
-# ATT: {nf} shlw %dx, %dx
+# ATT: {nf} shlw $1, %dx, %dx
# INTEL: {nf} shl dx, dx
0x62,0xf4,0x6d,0x1c,0xd1,0xe2
@@ -301,7 +301,7 @@
# INTEL: shl ecx, ecx
0x62,0xf4,0x74,0x18,0xd1,0xe1
-# ATT: {nf} shll %ecx, %ecx
+# ATT: {nf} shll $1, %ecx, %ecx
# INTEL: {nf} shl ecx, ecx
0x62,0xf4,0x74,0x1c,0xd1,0xe1
@@ -317,7 +317,7 @@
# INTEL: shl r9, r9
0x62,0xd4,0xb4,0x18,0xd1,0xe1
-# ATT: {nf} shlq %r9, %r9
+# ATT: {nf} shlq $1, %r9, %r9
# INTEL: {nf} shl r9, r9
0x62,0xd4,0xb4,0x1c,0xd1,0xe1
diff --git a/llvm/test/MC/Disassembler/X86/apx/shr.txt b/llvm/test/MC/Disassembler/X86/apx/shr.txt
index 1e7e1732b56fb..2ac2e32d46466 100644
--- a/llvm/test/MC/Disassembler/X86/apx/shr.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/shr.txt
@@ -141,7 +141,7 @@
# INTEL: shr bl, bl
0x62,0xf4,0x64,0x18,0xd0,0xeb
-# ATT: {nf} shrb %bl, %bl
+# ATT: {nf} shrb $1, %bl, %bl
# INTEL: {nf} shr bl, bl
0x62,0xf4,0x64,0x1c,0xd0,0xeb
@@ -285,7 +285,7 @@
# INTEL: shr dx, dx
0x62,0xf4,0x6d,0x18,0xd1,0xea
-# ATT: {nf} shrw %dx, %dx
+# ATT: {nf} shrw $1, %dx, %dx
# INTEL: {nf} shr dx, dx
0x62,0xf4,0x6d,0x1c,0xd1,0xea
@@ -301,7 +301,7 @@
# INTEL: shr ecx, ecx
0x62,0xf4,0x74,0x18,0xd1,0xe9
-# ATT: {nf} shrl %ecx, %ecx
+# ATT: {nf} shrl $1, %ecx, %ecx
# INTEL: {nf} shr ecx, ecx
0x62,0xf4,0x74,0x1c,0xd1,0xe9
@@ -317,7 +317,7 @@
# INTEL: shr r9, r9
0x62,0xd4,0xb4,0x18,0xd1,0xe9
-# ATT: {nf} shrq %r9, %r9
+# ATT: {nf} shrq $1, %r9, %r9
# INTEL: {nf} shr r9, r9
0x62,0xd4,0xb4,0x1c,0xd1,0xe9
diff --git a/llvm/test/MC/X86/apx/rol-att.s b/llvm/test/MC/X86/apx/rol-att.s
index 30c1c3a9ffe4c..494d86e61053d 100644
--- a/llvm/test/MC/X86/apx/rol-att.s
+++ b/llvm/test/MC/X86/apx/rol-att.s
@@ -210,9 +210,9 @@
# CHECK: rolw %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x18,0xd1,0xc2]
rolw %dx, %dx
-# CHECK: {nf} rolw %dx, %dx
+# CHECK: {nf} rolw $1, %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xc2]
- {nf} rolw %dx, %dx
+ {nf} rolw $1, %dx, %dx
# CHECK: {evex} roll %ecx
# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xc1]
{evex} roll %ecx
@@ -222,9 +222,9 @@
# CHECK: roll %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x18,0xd1,0xc1]
roll %ecx, %ecx
-# CHECK: {nf} roll %ecx, %ecx
+# CHECK: {nf} roll $1, %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x1c,0xd1,0xc1]
- {nf} roll %ecx, %ecx
+ {nf} roll $1, %ecx, %ecx
# CHECK: {evex} rolq %r9
# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0xc1]
{evex} rolq %r9
@@ -234,9 +234,9 @@
# CHECK: rolq %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xd1,0xc1]
rolq %r9, %r9
-# CHECK: {nf} rolq %r9, %r9
+# CHECK: {nf} rolq $1, %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xd1,0xc1]
- {nf} rolq %r9, %r9
+ {nf} rolq $1, %r9, %r9
# CHECK: {evex} rolb 291(%r8,%rax,4)
# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0x84,0x80,0x23,0x01,0x00,0x00]
{evex} rolb 291(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/rol-encopt.s b/llvm/test/MC/X86/apx/rol-encopt.s
index d154779d1f626..b4e94c125eb6c 100644
--- a/llvm/test/MC/X86/apx/rol-encopt.s
+++ b/llvm/test/MC/X86/apx/rol-encopt.s
@@ -36,16 +36,16 @@
# CHECK: rolq %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xc0]
rolq $1, %rax, %rbx
-# CHECK: {nf} rolb %al, %bl
+# CHECK: {nf} rolb $1, %al, %bl
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd0,0xc0]
{nf} rolb $1, %al, %bl
-# CHECK: {nf} rolw %ax, %bx
+# CHECK: {nf} rolw $1, %ax, %bx
# CHECK: encoding: [0x62,0xf4,0x65,0x1c,0xd1,0xc0]
{nf} rolw $1, %ax, %bx
-# CHECK: {nf} roll %eax, %ebx
+# CHECK: {nf} roll $1, %eax, %ebx
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd1,0xc0]
{nf} roll $1, %eax, %ebx
-# CHECK: {nf} rolq %rax, %rbx
+# CHECK: {nf} rolq $1, %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x1c,0xd1,0xc0]
{nf} rolq $1, %rax, %rbx
# CHECK: {evex} rolb 123(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/ror-att.s b/llvm/test/MC/X86/apx/ror-att.s
index aa877f20e4e5d..70338ad7d20e1 100644
--- a/llvm/test/MC/X86/apx/ror-att.s
+++ b/llvm/test/MC/X86/apx/ror-att.s
@@ -210,9 +210,9 @@
# CHECK: rorw %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x18,0xd1,0xca]
rorw %dx, %dx
-# CHECK: {nf} rorw %dx, %dx
+# CHECK: {nf} rorw $1, %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xca]
- {nf} rorw %dx, %dx
+ {nf} rorw $1, %dx, %dx
# CHECK: {evex} rorl %ecx
# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xc9]
{evex} rorl %ecx
@@ -222,9 +222,9 @@
# CHECK: rorl %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x18,0xd1,0xc9]
rorl %ecx, %ecx
-# CHECK: {nf} rorl %ecx, %ecx
+# CHECK: {nf} rorl $1, %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x1c,0xd1,0xc9]
- {nf} rorl %ecx, %ecx
+ {nf} rorl $1, %ecx, %ecx
# CHECK: {evex} rorq %r9
# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0xc9]
{evex} rorq %r9
@@ -234,9 +234,9 @@
# CHECK: rorq %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xd1,0xc9]
rorq %r9, %r9
-# CHECK: {nf} rorq %r9, %r9
+# CHECK: {nf} rorq $1, %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xd1,0xc9]
- {nf} rorq %r9, %r9
+ {nf} rorq $1, %r9, %r9
# CHECK: {evex} rorb 291(%r8,%rax,4)
# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0x8c,0x80,0x23,0x01,0x00,0x00]
{evex} rorb 291(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/ror-encopt.s b/llvm/test/MC/X86/apx/ror-encopt.s
index f1033a60f7d5c..c86bd99a66f65 100644
--- a/llvm/test/MC/X86/apx/ror-encopt.s
+++ b/llvm/test/MC/X86/apx/ror-encopt.s
@@ -36,16 +36,16 @@
# CHECK: rorq %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xc8]
rorq $1, %rax, %rbx
-# CHECK: {nf} rorb %al, %bl
+# CHECK: {nf} rorb $1, %al, %bl
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd0,0xc8]
{nf} rorb $1, %al, %bl
-# CHECK: {nf} rorw %ax, %bx
+# CHECK: {nf} rorw $1, %ax, %bx
# CHECK: encoding: [0x62,0xf4,0x65,0x1c,0xd1,0xc8]
{nf} rorw $1, %ax, %bx
-# CHECK: {nf} rorl %eax, %ebx
+# CHECK: {nf} rorl $1, %eax, %ebx
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd1,0xc8]
{nf} rorl $1, %eax, %ebx
-# CHECK: {nf} rorq %rax, %rbx
+# CHECK: {nf} rorq $1, %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x1c,0xd1,0xc8]
{nf} rorq $1, %rax, %rbx
# CHECK: {evex} rorb 123(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/sar-att.s b/llvm/test/MC/X86/apx/sar-att.s
index 9ab96f277bc70..eb80497b7291c 100644
--- a/llvm/test/MC/X86/apx/sar-att.s
+++ b/llvm/test/MC/X86/apx/sar-att.s
@@ -210,9 +210,9 @@
# CHECK: sarw %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x18,0xd1,0xfa]
sarw %dx, %dx
-# CHECK: {nf} sarw %dx, %dx
+# CHECK: {nf} sarw $1, %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xfa]
- {nf} sarw %dx, %dx
+ {nf} sarw $1, %dx, %dx
# CHECK: {evex} sarl %ecx
# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xf9]
{evex} sarl %ecx
@@ -222,9 +222,9 @@
# CHECK: sarl %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x18,0xd1,0xf9]
sarl %ecx, %ecx
-# CHECK: {nf} sarl %ecx, %ecx
+# CHECK: {nf} sarl $1, %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x1c,0xd1,0xf9]
- {nf} sarl %ecx, %ecx
+ {nf} sarl $1, %ecx, %ecx
# CHECK: {evex} sarq %r9
# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0xf9]
{evex} sarq %r9
@@ -234,9 +234,9 @@
# CHECK: sarq %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xd1,0xf9]
sarq %r9, %r9
-# CHECK: {nf} sarq %r9, %r9
+# CHECK: {nf} sarq $1, %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xd1,0xf9]
- {nf} sarq %r9, %r9
+ {nf} sarq $1, %r9, %r9
# CHECK: {evex} sarb 291(%r8,%rax,4)
# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0xbc,0x80,0x23,0x01,0x00,0x00]
{evex} sarb 291(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/sar-encopt.s b/llvm/test/MC/X86/apx/sar-encopt.s
index 1399536bf1f7c..a85a17ff706ee 100644
--- a/llvm/test/MC/X86/apx/sar-encopt.s
+++ b/llvm/test/MC/X86/apx/sar-encopt.s
@@ -36,16 +36,16 @@
# CHECK: sarq %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xf8]
sarq $1, %rax, %rbx
-# CHECK: {nf} sarb %al, %bl
+# CHECK: {nf} sarb $1, %al, %bl
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd0,0xf8]
{nf} sarb $1, %al, %bl
-# CHECK: {nf} sarw %ax, %bx
+# CHECK: {nf} sarw $1, %ax, %bx
# CHECK: encoding: [0x62,0xf4,0x65,0x1c,0xd1,0xf8]
{nf} sarw $1, %ax, %bx
-# CHECK: {nf} sarl %eax, %ebx
+# CHECK: {nf} sarl $1, %eax, %ebx
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd1,0xf8]
{nf} sarl $1, %eax, %ebx
-# CHECK: {nf} sarq %rax, %rbx
+# CHECK: {nf} sarq $1, %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x1c,0xd1,0xf8]
{nf} sarq $1, %rax, %rbx
# CHECK: {evex} sarb 123(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/shl-att.s b/llvm/test/MC/X86/apx/shl-att.s
index d86f6cf05a7db..a523c0767ac3b 100644
--- a/llvm/test/MC/X86/apx/shl-att.s
+++ b/llvm/test/MC/X86/apx/shl-att.s
@@ -210,9 +210,9 @@
# CHECK: shlw %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x18,0xd1,0xe2]
shlw %dx, %dx
-# CHECK: {nf} shlw %dx, %dx
+# CHECK: {nf} shlw $1, %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xe2]
- {nf} shlw %dx, %dx
+ {nf} shlw $1, %dx, %dx
# CHECK: {evex} shll %ecx
# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xe1]
{evex} shll %ecx
@@ -222,9 +222,9 @@
# CHECK: shll %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x18,0xd1,0xe1]
shll %ecx, %ecx
-# CHECK: {nf} shll %ecx, %ecx
+# CHECK: {nf} shll $1, %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x1c,0xd1,0xe1]
- {nf} shll %ecx, %ecx
+ {nf} shll $1, %ecx, %ecx
# CHECK: {evex} shlq %r9
# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0xe1]
{evex} shlq %r9
@@ -234,9 +234,9 @@
# CHECK: shlq %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xd1,0xe1]
shlq %r9, %r9
-# CHECK: {nf} shlq %r9, %r9
+# CHECK: {nf} shlq $1, %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xd1,0xe1]
- {nf} shlq %r9, %r9
+ {nf} shlq $1, %r9, %r9
# CHECK: {evex} shlb 291(%r8,%rax,4)
# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0xa4,0x80,0x23,0x01,0x00,0x00]
{evex} shlb 291(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/shl-encopt.s b/llvm/test/MC/X86/apx/shl-encopt.s
index 0feeddc140064..5225c867a970d 100644
--- a/llvm/test/MC/X86/apx/shl-encopt.s
+++ b/llvm/test/MC/X86/apx/shl-encopt.s
@@ -36,16 +36,16 @@
# CHECK: shlq %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xe0]
shlq $1, %rax, %rbx
-# CHECK: {nf} shlb %al, %bl
+# CHECK: {nf} shlb $1, %al, %bl
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd0,0xe0]
{nf} shlb $1, %al, %bl
-# CHECK: {nf} shlw %ax, %bx
+# CHECK: {nf} shlw $1, %ax, %bx
# CHECK: encoding: [0x62,0xf4,0x65,0x1c,0xd1,0xe0]
{nf} shlw $1, %ax, %bx
-# CHECK: {nf} shll %eax, %ebx
+# CHECK: {nf} shll $1, %eax, %ebx
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd1,0xe0]
{nf} shll $1, %eax, %ebx
-# CHECK: {nf} shlq %rax, %rbx
+# CHECK: {nf} shlq $1, %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x1c,0xd1,0xe0]
{nf} shlq $1, %rax, %rbx
# CHECK: {evex} shlb 123(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/shr-att.s b/llvm/test/MC/X86/apx/shr-att.s
index 86656c325de2a..934536422d199 100644
--- a/llvm/test/MC/X86/apx/shr-att.s
+++ b/llvm/test/MC/X86/apx/shr-att.s
@@ -210,9 +210,9 @@
# CHECK: shrw %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x18,0xd1,0xea]
shrw %dx, %dx
-# CHECK: {nf} shrw %dx, %dx
+# CHECK: {nf} shrw $1, %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xea]
- {nf} shrw %dx, %dx
+ {nf} shrw $1, %dx, %dx
# CHECK: {evex} shrl %ecx
# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xe9]
{evex} shrl %ecx
@@ -222,9 +222,9 @@
# CHECK: shrl %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x18,0xd1,0xe9]
shrl %ecx, %ecx
-# CHECK: {nf} shrl %ecx, %ecx
+# CHECK: {nf} shrl $1, %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x1c,0xd1,0xe9]
- {nf} shrl %ecx, %ecx
+ {nf} shrl $1, %ecx, %ecx
# CHECK: {evex} shrq %r9
# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0xe9]
{evex} shrq %r9
@@ -234,9 +234,9 @@
# CHECK: shrq %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xd1,0xe9]
shrq %r9, %r9
-# CHECK: {nf} shrq %r9, %r9
+# CHECK: {nf} shrq $1, %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xd1,0xe9]
- {nf} shrq %r9, %r9
+ {nf} shrq $1, %r9, %r9
# CHECK: {evex} shrb 291(%r8,%rax,4)
# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0xac,0x80,0x23,0x01,0x00,0x00]
{evex} shrb 291(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/shr-encopt.s b/llvm/test/MC/X86/apx/shr-encopt.s
index 97b6b70086573..b8ec4c18b685c 100644
--- a/llvm/test/MC/X86/apx/shr-encopt.s
+++ b/llvm/test/MC/X86/apx/shr-encopt.s
@@ -36,16 +36,16 @@
# CHECK: shrq %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xe8]
shrq $1, %rax, %rbx
-# CHECK: {nf} shrb %al, %bl
+# CHECK: {nf} shrb $1, %al, %bl
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd0,0xe8]
{nf} shrb $1, %al, %bl
-# CHECK: {nf} shrw %ax, %bx
+# CHECK: {nf} shrw $1, %ax, %bx
# CHECK: encoding: [0x62,0xf4,0x65,0x1c,0xd1,0xe8]
{nf} shrw $1, %ax, %bx
-# CHECK: {nf} shrl %eax, %ebx
+# CHECK: {nf} shrl $1, %eax, %ebx
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd1,0xe8]
{nf} shrl $1, %eax, %ebx
-# CHECK: {nf} shrq %rax, %rbx
+# CHECK: {nf} shrq $1, %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x1c,0xd1,0xe8]
{nf} shrq $1, %rax, %rbx
# CHECK: {evex} shrb 123(%r8,%rax,4)
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