[llvm] [RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI (PR #181601)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 16 21:02:23 PST 2026
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/181601
>From 37b186677b58a86e21a61328735ab8c1224e8926 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 16 Feb 2026 13:41:10 +0800
Subject: [PATCH 1/4] [RISCV] Make ElementsDependOn opt-in instead of opt-out.
NFCI
RISCVVectorPeephole and RISCVVLOptimizer use the ElementsDependOn field to know if it's safe to change the VL of a vector instruction.
By default instructions are EltDepsNone, i.e. RISCVVectorPeephole::tryReduceVL will reduce its VL by default, but we might forget to mark unsafe instructions in newer extensions. This patch changes the default to EltDepsVLMask and instead explicitly marks any instructions which want to have their VL reduced.
There is an assert in RISCVVLOptimizer::isCandidate that ensures that all previously isSupported instructions are still marked correctly.
---
llvm/lib/Target/RISCV/RISCVInstrFormats.td | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 84 +++++++++++++------
llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td | 3 +-
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td | 2 -
.../Target/RISCV/RISCVInstrInfoXSpacemiT.td | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td | 4 +-
llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td | 4 +-
llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td | 4 +
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 6 +-
9 files changed, 74 insertions(+), 37 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 9ecc2f60262c8..cf98f9bf3b23b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -253,7 +253,7 @@ class RVInstCommon<dag outs, dag ins, string opcodestr, string argstr,
// of VL (e.g. vslide1down.vx), and others may depend on the VL and mask
// (e.g. vredsum.vs, viota.m). Mark these instructions so that peepholes avoid
// changing their VL and/or mask.
- EltDeps ElementsDependOn = EltDepsNone;
+ EltDeps ElementsDependOn = EltDepsVLMask;
let TSFlags{22} = ElementsDependOn.VL;
let TSFlags{23} = ElementsDependOn.Mask;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 7280823b6735b..fd9cefa4e48df 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1122,6 +1122,7 @@ def VSETVL : RVInstVSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
} // hasSideEffects = 1, mayLoad = 0, mayStore = 0
} // Predicates = [HasVInstructions]
+let ElementsDependOn = EltDepsNone in
foreach eew = [8, 16, 32, 64] in {
defvar w = !cast<RISCVWidth>("LSWidth" # eew);
@@ -1150,6 +1151,7 @@ foreach eew = [8, 16, 32, 64] in {
}
let Predicates = [HasVInstructions] in {
+let ElementsDependOn = EltDepsNone in
def VLM_V : VUnitStrideMaskLoad<"vlm.v">,
Sched<[WriteVLDM_WorstCase, ReadVLDX]>;
def VSM_V : VUnitStrideMaskStore<"vsm.v">,
@@ -1174,13 +1176,16 @@ def : InstAlias<"vl8r.v $vd, $rs1", (VL8RE8_V VRM8:$vd, GPRMemZeroOffset:$rs1)>;
let Predicates = [HasVInstructions] in {
// Vector Single-Width Integer Add and Subtract
+let ElementsDependOn = EltDepsNone in {
defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>;
defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>;
defm VRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>;
+} // ElementsDependOn = EltDepsNone
def : InstAlias<"vneg.v $vd, $vs$vm", (VRSUB_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
def : InstAlias<"vneg.v $vd, $vs", (VRSUB_VX VR:$vd, VR:$vs, X0, zero_reg)>;
+let ElementsDependOn = EltDepsNone in {
// Vector Widening Integer Add/Subtract
// Refer to 11.2 Widening Vector Arithmetic Instructions
// The destination vector register group cannot overlap a source vector
@@ -1204,6 +1209,7 @@ defm VWADD_W : VALU_MV_V_X<"vwadd", 0b110101, "w">;
defm VWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, "w">;
} // RVVConstraint = WidenW
} // Constraints = "@earlyclobber $vd", DestEEW = EEWSEWx2
+} // ElementsDependOn = EltDepsNone
def : InstAlias<"vwcvt.x.x.v $vd, $vs$vm",
(VWADD_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
@@ -1214,6 +1220,8 @@ def : InstAlias<"vwcvtu.x.x.v $vd, $vs$vm",
def : InstAlias<"vwcvtu.x.x.v $vd, $vs",
(VWADDU_VX VR:$vd, VR:$vs, X0, zero_reg)>;
+let ElementsDependOn = EltDepsNone in {
+
// Vector Integer Extension
defm VZEXT_VF8 : VALU_MV_VS2<"vzext.vf8", 0b010010, 0b00010>;
defm VSEXT_VF8 : VALU_MV_VS2<"vsext.vf8", 0b010010, 0b00011>;
@@ -1238,11 +1246,15 @@ defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>;
defm VOR_V : VALU_IV_V_X_I<"vor", 0b001010>;
defm VXOR_V : VALU_IV_V_X_I<"vxor", 0b001011>;
+} // ElementsDependOn = EltDepsNone
+
def : InstAlias<"vnot.v $vd, $vs$vm",
(VXOR_VI VR:$vd, VR:$vs, -1, VMaskOp:$vm)>;
def : InstAlias<"vnot.v $vd, $vs",
(VXOR_VI VR:$vd, VR:$vs, -1, zero_reg)>;
+let ElementsDependOn = EltDepsNone in {
+
// Vector Single-Width Bit Shift Instructions
defm VSLL_V : VSHT_IV_V_X_I<"vsll", 0b100101>;
defm VSRL_V : VSHT_IV_V_X_I<"vsrl", 0b101000>;
@@ -1258,13 +1270,16 @@ defm VNSRL_W : VNSHT_IV_V_X_I<"vnsrl", 0b101100>;
defm VNSRA_W : VNSHT_IV_V_X_I<"vnsra", 0b101101>;
} // Constraints = "@earlyclobber $vd"
+} // ElementsDependOn = EltDepsNone
+
def : InstAlias<"vncvt.x.x.w $vd, $vs$vm",
(VNSRL_WX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
def : InstAlias<"vncvt.x.x.w $vd, $vs",
(VNSRL_WX VR:$vd, VR:$vs, X0, zero_reg)>;
// Vector Integer Comparison Instructions
-let RVVConstraint = NoConstraint, DestEEW = EEW1 in {
+let RVVConstraint = NoConstraint, DestEEW = EEW1,
+ ElementsDependOn = EltDepsNone in {
defm VMSEQ_V : VCMP_IV_V_X_I<"vmseq", 0b011000>;
defm VMSNE_V : VCMP_IV_V_X_I<"vmsne", 0b011001>;
defm VMSLTU_V : VCMP_IV_V_X<"vmsltu", 0b011010>;
@@ -1284,6 +1299,8 @@ def : InstAlias<"vmsgeu.vv $vd, $va, $vb$vm",
def : InstAlias<"vmsge.vv $vd, $va, $vb$vm",
(VMSLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
+let ElementsDependOn = EltDepsNone in {
+
let isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0,
mayStore = 0, DestEEW = EEW1 in {
// For unsigned comparisons we need to special case 0 immediate to maintain
@@ -1400,9 +1417,15 @@ let Constraints = "@earlyclobber $vd" in {
defm VNCLIPU_W : VNCLP_IV_V_X_I<"vnclipu", 0b101110>;
defm VNCLIP_W : VNCLP_IV_V_X_I<"vnclip", 0b101111>;
} // Constraints = "@earlyclobber $vd"
+
+} // ElementsDependOn = EltDepsNone
+
} // Predicates = [HasVInstructions]
let Predicates = [HasVInstructionsAnyF] in {
+
+let ElementsDependOn = EltDepsNone in {
+
// Vector Single-Width Floating-Point Add/Subtract Instructions
let Uses = [FRM, VL, VTYPE], mayRaiseFPException = true in {
defm VFADD_V : VALU_FV_V_F<"vfadd", 0b000000>;
@@ -1482,6 +1505,8 @@ defm VFSGNJ_V : VSGNJ_FV_V_F<"vfsgnj", 0b001000>;
defm VFSGNJN_V : VSGNJ_FV_V_F<"vfsgnjn", 0b001001>;
defm VFSGNJX_V : VSGNJ_FV_V_F<"vfsgnjx", 0b001010>;
+} // ElementsDependOn = EltDepsNone
+
def : InstAlias<"vfneg.v $vd, $vs$vm",
(VFSGNJN_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>;
def : InstAlias<"vfneg.v $vd, $vs",
@@ -1492,20 +1517,23 @@ def : InstAlias<"vfabs.v $vd, $vs",
(VFSGNJX_VV VR:$vd, VR:$vs, VR:$vs, zero_reg)>;
// Vector Floating-Point Compare Instructions
-let RVVConstraint = NoConstraint, mayRaiseFPException = true, DestEEW = EEW1 in {
+let RVVConstraint = NoConstraint, mayRaiseFPException = true, DestEEW = EEW1,
+ ElementsDependOn = EltDepsNone in {
defm VMFEQ_V : VCMP_FV_V_F<"vmfeq", 0b011000>;
defm VMFNE_V : VCMP_FV_V_F<"vmfne", 0b011100>;
defm VMFLT_V : VCMP_FV_V_F<"vmflt", 0b011011>;
defm VMFLE_V : VCMP_FV_V_F<"vmfle", 0b011001>;
defm VMFGT_V : VCMP_FV_F<"vmfgt", 0b011101>;
defm VMFGE_V : VCMP_FV_F<"vmfge", 0b011111>;
-} // RVVConstraint = NoConstraint, mayRaiseFPException = true, DestEEW = EEW1
+} // RVVConstraint = NoConstraint, mayRaiseFPException = true, DestEEW = EEW1, ElementsDependOn = EltDepsNone
def : InstAlias<"vmfgt.vv $vd, $va, $vb$vm",
(VMFLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
def : InstAlias<"vmfge.vv $vd, $va, $vb$vm",
(VMFLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
+let ElementsDependOn = EltDepsNone in {
+
// Vector Floating-Point Classify Instruction
defm VFCLASS_V : VCLS_FV_VS2<"vfclass.v", 0b010011, 0b10000>;
@@ -1574,12 +1602,13 @@ defm VFNCVT_F_F_W : VNCVTF_FV_VS2<"vfncvt.f.f.w", 0b010010, 0b10100>;
}
defm VFNCVT_ROD_F_F_W : VNCVTF_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>;
} // Constraints = "@earlyclobber $vd", mayRaiseFPException = true
+} // ElementsDependOn = EltDepsNone
} // Predicates = HasVInstructionsAnyF]
let Predicates = [HasVInstructions] in {
// Vector Single-Width Integer Reduction Instructions
-let RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask in {
+let RVVConstraint = NoConstraint in {
defm VREDSUM : VRED_MV_V<"vredsum", 0b000000>;
defm VREDMAXU : VREDMINMAX_MV_V<"vredmaxu", 0b000110>;
defm VREDMAX : VREDMINMAX_MV_V<"vredmax", 0b000111>;
@@ -1588,23 +1617,23 @@ defm VREDMIN : VREDMINMAX_MV_V<"vredmin", 0b000101>;
defm VREDAND : VRED_MV_V<"vredand", 0b000001>;
defm VREDOR : VRED_MV_V<"vredor", 0b000010>;
defm VREDXOR : VRED_MV_V<"vredxor", 0b000011>;
-} // RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask
+} // RVVConstraint = NoConstraint
// Vector Widening Integer Reduction Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask, DestEEW = EEWSEWx2 in {
+let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, DestEEW = EEWSEWx2 in {
// Set earlyclobber for following instructions for second and mask operands.
// This has the downside that the earlyclobber constraint is too coarse and
// will impose unnecessary restrictions by not allowing the destination to
// overlap with the first (wide) operand.
defm VWREDSUMU : VWRED_IV_V<"vwredsumu", 0b110000>;
defm VWREDSUM : VWRED_IV_V<"vwredsum", 0b110001>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask, DestEEW = EEWSEWx2
+} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, DestEEW = EEWSEWx2
} // Predicates = [HasVInstructions]
let Predicates = [HasVInstructionsAnyF] in {
// Vector Single-Width Floating-Point Reduction Instructions
-let RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask in {
+let RVVConstraint = NoConstraint in {
let Uses = [FRM, VL, VTYPE], mayRaiseFPException = true in {
defm VFREDOSUM : VREDO_FV_V<"vfredosum", 0b000011>;
defm VFREDUSUM : VRED_FV_V<"vfredusum", 0b000001>;
@@ -1613,12 +1642,12 @@ let mayRaiseFPException = true in {
defm VFREDMAX : VREDMINMAX_FV_V<"vfredmax", 0b000111>;
defm VFREDMIN : VREDMINMAX_FV_V<"vfredmin", 0b000101>;
}
-} // RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask
+} // RVVConstraint = NoConstraint
def : MnemonicAlias<"vfredsum.vs", "vfredusum.vs">;
// Vector Widening Floating-Point Reduction Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask, DestEEW = EEWSEWx2 in {
+let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, DestEEW = EEWSEWx2 in {
// Set earlyclobber for following instructions for second and mask operands.
// This has the downside that the earlyclobber constraint is too coarse and
// will impose unnecessary restrictions by not allowing the destination to
@@ -1627,14 +1656,15 @@ let Uses = [FRM, VL, VTYPE], mayRaiseFPException = true in {
defm VFWREDOSUM : VWREDO_FV_V<"vfwredosum", 0b110011>;
defm VFWREDUSUM : VWRED_FV_V<"vfwredusum", 0b110001>;
}
-} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask, DestEEW = EEWSEWx2
+} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, DestEEW = EEWSEWx2
def : MnemonicAlias<"vfwredsum.vs", "vfwredusum.vs">;
} // Predicates = [HasVInstructionsAnyF]
let Predicates = [HasVInstructions] in {
// Vector Mask-Register Logical Instructions
-let RVVConstraint = NoConstraint, DestEEW = EEW1 in {
+let RVVConstraint = NoConstraint, DestEEW = EEW1,
+ ElementsDependOn = EltDepsNone in {
defm VMAND_M : VMALU_MV_Mask<"vmand", 0b011001, "m">;
defm VMNAND_M : VMALU_MV_Mask<"vmnand", 0b011101, "m">;
defm VMANDN_M : VMALU_MV_Mask<"vmandn", 0b011000, "m">;
@@ -1657,8 +1687,7 @@ def : InstAlias<"vmnot.m $vd, $vs",
def : MnemonicAlias<"vmandnot.mm", "vmandn.mm">;
def : MnemonicAlias<"vmornot.mm", "vmorn.mm">;
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
- ElementsDependOn = EltDepsVLMask in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
// Vector mask population count vcpop
def VCPOP_M : RVInstVUnaryRd<0b010000, 0b10000, OPMVV, (outs GPR:$rd),
@@ -1672,7 +1701,7 @@ def VFIRST_M : RVInstVUnaryRd<0b010000, 0b10001, OPMVV, (outs GPR:$rd),
"vfirst.m", "$rd, $vs2$vm">,
SchedUnaryMC<"WriteVMFFSV", "ReadVMFFSV">;
-} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, RVVConstraint = NoConstraint
def : MnemonicAlias<"vpopc.m", "vcpop.m">;
@@ -1692,7 +1721,8 @@ defm VIOTA_M : VIOTA_MV_V<"viota.m", 0b010100, 0b10000>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota, ElementsDependOn = EltDepsMask
// Vector Element Index Instruction
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+ ElementsDependOn = EltDepsNone in {
def VID_V : RVInstVUnary<0b010100, 0b10001, OPMVV, (outs VR:$vd),
(ins VMaskOp:$vm), "vid.v", "$vd$vm">,
@@ -1717,13 +1747,14 @@ def VMV_S_X : RVInstVX<0b010000, OPMVX, (outs VR:$vd_wb),
let RVVConstraint = NoConstraint;
}
-} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, ElementsDependOn = EltDepsNone
} // Predicates = [HasVInstructions]
let Predicates = [HasVInstructionsAnyF] in {
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1 in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1,
+ ElementsDependOn = EltDepsNone in {
// Floating-Point Scalar Move Instructions
def VFMV_F_S : RVInstVUnaryRd<0b010000, 0b00000, OPFVV, (outs FPR32:$rd),
(ins VR:$vs2), "vfmv.f.s", "$rd, $vs2">,
@@ -1745,18 +1776,20 @@ def VFMV_S_F : RVInstVX<0b010000, OPFVF, (outs VR:$vd_wb),
let Predicates = [HasVInstructions] in {
// Vector Slide Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
+let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp,
+ ElementsDependOn = EltDepsNone in {
defm VSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110, /*slidesUp=*/true>;
defm VSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
-let ReadsPastVL = 1 in
+let ReadsPastVL = 1, ElementsDependOn = EltDepsNone in
defm VSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111, /*slidesUp=*/false>;
let ElementsDependOn = EltDepsVL, ReadsPastVL = 1 in
defm VSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111>;
} // Predicates = [HasVInstructions]
let Predicates = [HasVInstructionsAnyF] in {
-let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
+let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp,
+ ElementsDependOn = EltDepsNone in {
defm VFSLIDE1UP_V : VSLD1_FV_F<"vfslide1up", 0b001110>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
let ElementsDependOn = EltDepsVL, ReadsPastVL = 1 in
@@ -1765,18 +1798,19 @@ defm VFSLIDE1DOWN_V : VSLD1_FV_F<"vfslide1down", 0b001111>;
let Predicates = [HasVInstructions] in {
// Vector Register Gather Instruction
-let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather, ReadsPastVL = 1 in {
+let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather,
+ ReadsPastVL = 1, ElementsDependOn = EltDepsNone in {
defm VRGATHER_V : VGTR_IV_V_X_I<"vrgather", 0b001100>;
def VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">,
SchedBinaryMC<"WriteVRGatherEI16VV",
"ReadVRGatherEI16VV_data",
"ReadVRGatherEI16VV_index">;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather, ReadsPastVL = 1
+} // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather, ReadsPastVL = 1, ElementsDependOn = EltDepsNone
// Vector Compress Instruction
-let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress, ElementsDependOn = EltDepsVLMask in {
+let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in {
defm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress, ElementsDependOn = EltDepsVLMask
+} // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1,
RVVConstraint = NoConstraint in {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
index daf8550e4cb45..59eadfeaa78c8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
@@ -58,7 +58,8 @@ class CustomRivosXVI<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
let Predicates = [HasVendorXRivosVizip], DecoderNamespace = "XRivos",
Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather,
- Inst<6-0> = OPC_CUSTOM_2.Value, ReadsPastVL = 1 in {
+ Inst<6-0> = OPC_CUSTOM_2.Value, ReadsPastVL = 1,
+ ElementsDependOn = EltDepsNone in {
defm RI_VZIPEVEN_V : VALU_IV_V<"ri.vzipeven", 0b001100>;
defm RI_VZIPODD_V : VALU_IV_V<"ri.vzipodd", 0b011100>;
defm RI_VZIP2A_V : VALU_IV_V<"ri.vzip2a", 0b000100>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index bc65db1f77ffb..c6d1d99a9280a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -130,7 +130,6 @@ class RVInstVCCustom2Base<VCIXInfo info>
let Uses = [VL, VTYPE];
let Constraints = info.Constraints;
let RVVConstraint = info.RVVConstraint;
- let ElementsDependOn = EltDepsVLMask;
let ReadsPastVL = 1;
}
@@ -232,7 +231,6 @@ class CustomSiFiveVMACC<bits<6> funct6, RISCVVFormat opv, string opcodestr>
let Constraints = "$vd = $vd_wb";
let RVVConstraint = NoConstraint;
- let ElementsDependOn = EltDepsVLMask;
let ReadsPastVL = true;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td
index 0f9b795069b98..d3db28686eda4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td
@@ -102,7 +102,7 @@ class RVInstSMTVDotSlide<SMTVEncoding2 funct2, SMTVEncoding2 sign, string opcode
let DecoderNamespace = "XSMT" in {
-let Predicates = [HasVendorXSMTVDot], ElementsDependOn = EltDepsVL in {
+let Predicates = [HasVendorXSMTVDot] in {
// Base vector dot product (no slide) instructions
// NOTE: Destination registers (vd) MUST be even-numbered (v0, v2, ..., v30)
// due to hardware alignment constraints. Using odd registers may cause undefined behavior.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
index c2b25c6294019..a73be41f57518 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
@@ -257,13 +257,13 @@ class THStoreUpdate<bits<5> funct5, string opcodestr>
//===----------------------------------------------------------------------===//
multiclass THVdotVMAQA_VX<string opcodestr, bits<6> funct6> {
- let RVVConstraint = WidenV, ElementsDependOn = EltDepsVLMask in
+ let RVVConstraint = WidenV in
def _VX : THVdotALUrVX<funct6, OPMVX, opcodestr # ".vx", EarlyClobber=1>;
}
multiclass THVdotVMAQA<string opcodestr, bits<6> funct6>
: THVdotVMAQA_VX<opcodestr, funct6> {
- let RVVConstraint = WidenV, ElementsDependOn = EltDepsVLMask in
+ let RVVConstraint = WidenV in
def _VV : THVdotALUrVV<funct6, OPMVX, opcodestr # ".vv", EarlyClobber=1>;
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
index 09c70ba72da29..64238460f7994 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
@@ -14,7 +14,7 @@
//===----------------------------------------------------------------------===//
// Instruction Definitions
//===----------------------------------------------------------------------===//
-let Predicates = [HasStdExtZvabd] in {
+let Predicates = [HasStdExtZvabd], ElementsDependOn = EltDepsNone in {
def VABS_V : VALUVs2<0b010010, 0b10000, OPMVV, "vabs.v">;
def VABD_VV : VALUVV<0b010001, OPMVV, "vabd.vv">;
@@ -24,7 +24,7 @@ let Predicates = [HasStdExtZvabd] in {
def VWABDA_VV : VALUVV<0b010101, OPMVV, "vwabda.vv">;
def VWABDAU_VV : VALUVV<0b010110, OPMVV, "vwabdau.vv">;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
-} // Predicates = [HasStdExtZvabd]
+} // Predicates = [HasStdExtZvabd], ElementsDependOn = EltDepsNone
//===----------------------------------------------------------------------===//
// Pseudos
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
index ca4b01d74fbb7..f1ded435f52d3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
@@ -17,6 +17,8 @@
// Instructions
//===----------------------------------------------------------------------===//
+let ElementsDependOn = EltDepsNone in {
+
let Predicates = [HasStdExtZvfbfminOrZvfofp8min],
Constraints = "@earlyclobber $vd",
mayRaiseFPException = true in {
@@ -32,6 +34,8 @@ let Predicates = [HasStdExtZvfbfwma],
defm VFWMACCBF16_V : VWMAC_FV_V_F<"vfwmaccbf16", 0b111011>;
}
+} // ElementsDependOn = EltDepsNone
+
//===----------------------------------------------------------------------===//
// Pseudo instructions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 3a5ddb8b2b994..2d67f33714c62 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -110,6 +110,8 @@ multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
// Instructions
//===----------------------------------------------------------------------===//
+let ElementsDependOn = EltDepsNone in {
+
let Predicates = [HasStdExtZvbb] in {
def VBREV_V : VALUVs2<0b010010, 0b01010, OPMVV, "vbrev.v">;
def VCLZ_V : VALUVs2<0b010010, 0b01100, OPMVV, "vclz.v">;
@@ -133,7 +135,7 @@ let Predicates = [HasStdExtZvkb] in {
defm VROR_V : VROR_IV_V_X_I<"vror", 0b010100>;
} // Predicates = [HasStdExtZvkb]
-let ElementsDependOn = EltDepsVLMask in {
+} // ElementsDependOn = EltDepsNone
let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {
def VGHSH_VV : PALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">,
@@ -191,8 +193,6 @@ let Predicates = [HasStdExtZvksh], RVVConstraint = VS2Constraint in {
SchedUnaryMC<"WriteVSM3MEV", "ReadVSM3MEV">;
} // Predicates = [HasStdExtZvksh]
-} // ElementsDependOn = EltDepsVLMask
-
//===----------------------------------------------------------------------===//
// Pseudo instructions
//===----------------------------------------------------------------------===//
>From 6566cdf5a0904d355aed271db5a5708eca04e415 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 16 Feb 2026 14:35:07 +0800
Subject: [PATCH 2/4] Add segmented instructions
---
llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index fd9cefa4e48df..98993eabe0ce0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1827,6 +1827,7 @@ foreach n = [1, 2, 4, 8] in {
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
} // Predicates = [HasVInstructions]
+let ElementsDependOn = EltDepsNone in {
let Predicates = [HasVInstructions] in {
foreach nfields=2-8 in {
foreach eew = [8, 16, 32] in {
@@ -1917,6 +1918,7 @@ let Predicates = [HasVInstructionsI64, IsRV64] in {
VSXSEGSchedMC<nfields, 64, isOrdered=1>;
}
} // Predicates = [HasVInstructionsI64, IsRV64]
+} // ElementsDependOn = EltDepsNone
include "RISCVInstrInfoVPseudos.td"
include "RISCVInstrInfoZvfbf.td"
>From 99f4571bc236b305e145cb5dc3ba1e6be7574120 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 16 Feb 2026 14:41:38 +0800
Subject: [PATCH 3/4] Add XRivosVisni
---
llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
index 59eadfeaa78c8..a712ec7088306 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
@@ -116,7 +116,8 @@ defm : RIVPatBinaryVL_VV<ri_vunzip2b_vl, "PseudoRI_VUNZIP2B">;
//===----------------------------------------------------------------------===//
let Predicates = [HasVendorXRivosVisni], DecoderNamespace = "XRivos",
- mayLoad = false, mayStore = false, hasSideEffects = false in {
+ mayLoad = false, mayStore = false, hasSideEffects = false,
+ ElementsDependOn = EltDepsNone in {
let vm = 0, vs2=0, Inst<6-0> = OPC_CUSTOM_2.Value,
isReMaterializable = 1, isAsCheapAsAMove = 1 in
>From da656c0ba81443f3ae980c9d27c5e6e157d6a05b Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Tue, 17 Feb 2026 13:02:07 +0800
Subject: [PATCH 4/4] Update comment
---
llvm/lib/Target/RISCV/RISCVInstrFormats.td | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index cf98f9bf3b23b..3013bfa6a549f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -250,9 +250,10 @@ class RVInstCommon<dag outs, dag ins, string opcodestr, string argstr,
let TSFlags{21-20} = TargetOverlapConstraintType;
// Most vector instructions are elementwise, but some may depend on the value
- // of VL (e.g. vslide1down.vx), and others may depend on the VL and mask
- // (e.g. vredsum.vs, viota.m). Mark these instructions so that peepholes avoid
- // changing their VL and/or mask.
+ // of vl (vslide1down.vx), and others may depend on the mask (viota.m) or both
+ // (vredsum.vs). By default we assume elements depend on both vl and the mask,
+ // but if marked as EltDepsNone or EltDepsMask then RISCVVLOptimizer will
+ // reduce its vl.
EltDeps ElementsDependOn = EltDepsVLMask;
let TSFlags{22} = ElementsDependOn.VL;
let TSFlags{23} = ElementsDependOn.Mask;
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