[llvm] AMDGPU/GlobalISel: Regbanklegalize rules for G_FMIN*/MAX* (PR #179778)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 16 20:56:07 PST 2026
https://github.com/vangthao95 updated https://github.com/llvm/llvm-project/pull/179778
>From 5a0731f9300bcf67249fd77acea1f371301eaf78 Mon Sep 17 00:00:00 2001
From: Vang Thao <vang.thao at amd.com>
Date: Wed, 4 Feb 2026 11:52:18 -0800
Subject: [PATCH 1/2] AMDGPU/GlobalISel: Regbanklegalize rules for G_FMIN*/MAX*
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 14 +
.../GlobalISel/clamp-fmed3-const-combine.ll | 4 +-
.../GlobalISel/clamp-minmax-const-combine.ll | 4 +-
.../GlobalISel/fmed3-min-max-const-combine.ll | 6 +-
llvm/test/CodeGen/AMDGPU/fmaximum.ll | 622 +++++++++++++-----
.../test/CodeGen/AMDGPU/fmed3-cast-combine.ll | 6 +-
llvm/test/CodeGen/AMDGPU/fmed3.ll | 10 +-
llvm/test/CodeGen/AMDGPU/fminimum.ll | 622 +++++++++++++-----
.../CodeGen/AMDGPU/fneg-combines-gfx1200.ll | 2 +-
llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll | 37 +-
llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll | 64 +-
llvm/test/CodeGen/AMDGPU/mad-mix.ll | 14 +-
llvm/test/CodeGen/AMDGPU/minimummaximum.ll | 4 +-
llvm/test/CodeGen/AMDGPU/minmax.ll | 12 +-
.../test/CodeGen/AMDGPU/vector-reduce-fmax.ll | 16 +-
.../test/CodeGen/AMDGPU/vector-reduce-fmin.ll | 16 +-
.../CodeGen/AMDGPU/vector-reduce-fminimum.ll | 4 +-
17 files changed, 1023 insertions(+), 434 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 20c7457eb7f43..cfe653428228f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1229,6 +1229,20 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}});
+ addRulesForGOpcs({G_FMINIMUM, G_FMAXIMUM, G_FMINNUM_IEEE, G_FMAXNUM_IEEE,
+ G_FMINNUM, G_FMAXNUM},
+ Standard)
+ .Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
+ .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
+ .Uni(S64, {{UniInVgprS64}, {Vgpr64, Vgpr64}})
+ .Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}})
+ .Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16}})
+ .Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}})
+ .Uni(S16, {{Sgpr16}, {Sgpr16, Sgpr16}}, hasSALUFloat)
+ .Uni(S16, {{UniInVgprS16}, {Vgpr16, Vgpr16}}, !hasSALUFloat)
+ .Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}}, hasSALUFloat)
+ .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}}, !hasSALUFloat);
+
addRulesForGOpcs({G_FPTRUNC})
.Any({{DivS16, S32}, {{Vgpr16}, {Vgpr32}}})
.Any({{UniS32, S64}, {{UniInVgprS32}, {Vgpr64}}})
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
index bdf54457b7159..23f5ae4f59005 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX12 %s
define float @test_fmed3_f32_known_nnan_ieee_true(float %a) #0 {
; GFX10-LABEL: test_fmed3_f32_known_nnan_ieee_true:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
index 8705647e36fe1..0315bd86feeda 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX12 %s
define float @test_min_max_ValK0_K1_f32(float %a) #0 {
; GFX10-LABEL: test_min_max_ValK0_K1_f32:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
index 696a87b9d0b4d..b754bb6081c31 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX12 %s
define float @test_min_max_ValK0_K1_f32(float %a) #0 {
; GFX10-LABEL: test_min_max_ValK0_K1_f32:
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum.ll b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
index 0283b5ff5d439..b264bf93d289b 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define amdgpu_ps float @test_fmaximum_f32_vv(float %a, float %b) {
; GFX9-LABEL: test_fmaximum_f32_vv:
@@ -24,14 +24,28 @@ define amdgpu_ps float @test_fmaximum_f32_vv(float %a, float %b) {
}
define amdgpu_ps float @test_fmaximum_f32_ss(float inreg %a, float inreg %b) {
-; GFX9-LABEL: test_fmaximum_f32_ss:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v0, s1
-; GFX9-NEXT: v_max_f32_e32 v1, s0, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GFX9-NEXT: ; return to shader part epilog
+; GFX9-SDAG-LABEL: test_fmaximum_f32_ss:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-SDAG-NEXT: v_max_f32_e32 v1, s0, v0
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX9-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX9-GISEL-LABEL: test_fmaximum_f32_ss:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_max_f32_e32 v1, s0, v0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s0, s0, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, s1, 0x7fc00000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fmaximum_f32_ss:
; GFX12: ; %bb.0:
@@ -127,18 +141,42 @@ define amdgpu_ps <2 x float> @test_fmaximum_v2f32(<2 x float> %a, <2 x float> %b
}
define amdgpu_ps <2 x float> @test_fmaximum_v2f32_ss(<2 x float> inreg %a, <2 x float> inreg %b) {
-; GFX9-LABEL: test_fmaximum_v2f32_ss:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_max_f32_e32 v1, s0, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: v_max_f32_e32 v3, s1, v1
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s1, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; GFX9-NEXT: ; return to shader part epilog
+; GFX9-SDAG-LABEL: test_fmaximum_v2f32_ss:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-SDAG-NEXT: v_max_f32_e32 v1, s0, v0
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-SDAG-NEXT: v_max_f32_e32 v3, s1, v1
+; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, s1, v1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; GFX9-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX9-GISEL-LABEL: test_fmaximum_v2f32_ss:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_max_f32_e32 v1, s0, v0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s0, s0, 1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, s1, v0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, s2, 0x7fc00000
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_max_f32_e32 v1, s1, v0
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s1, s1, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, s2, 0x7fc00000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fmaximum_v2f32_ss:
; GFX12: ; %bb.0:
@@ -315,14 +353,28 @@ define amdgpu_ps half @test_fmaximum_f16_vv(half %a, half %b) {
}
define amdgpu_ps half @test_fmaximum_f16_ss(half inreg %a, half inreg %b) {
-; GFX9-LABEL: test_fmaximum_f16_ss:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v0, s1
-; GFX9-NEXT: v_max_f16_e32 v1, s0, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x7e00
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GFX9-NEXT: ; return to shader part epilog
+; GFX9-SDAG-LABEL: test_fmaximum_f16_ss:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-SDAG-NEXT: v_max_f16_e32 v1, s0, v0
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7e00
+; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX9-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX9-GISEL-LABEL: test_fmaximum_f16_ss:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_max_f16_e32 v1, s0, v0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s0, s0, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, s1, 0x7e00
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fmaximum_f16_ss:
; GFX12: ; %bb.0:
@@ -389,16 +441,25 @@ define amdgpu_ps <2 x half> @test_fmaximum_v2f16_ss(<2 x half> inreg %a, <2 x ha
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX9-GISEL-NEXT: s_lshr_b32 s1, s1, 16
-; GFX9-GISEL-NEXT: s_lshr_b32 s2, s0, 16
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s1
; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s0, v0
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s2, v2
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x7e00
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], s0, v0
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-GISEL-NEXT: s_lshr_b32 s3, s0, 16
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s3, v0
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX9-GISEL-NEXT: s_lshr_b32 s3, s2, 16
+; GFX9-GISEL-NEXT: s_and_b32 s0, s0, 1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, s2, 0x7e00
+; GFX9-GISEL-NEXT: s_and_b32 s1, s1, 1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, s3, 0x7e00
+; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fmaximum_v2f16_ss:
@@ -428,16 +489,19 @@ define amdgpu_ps <3 x half> @test_fmaximum_v3f16_vv(<3 x half> %a, <3 x half> %b
; GFX9-GISEL-LABEL: test_fmaximum_v3f16_vv:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_pk_max_f16 v4, v0, v2
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x7e00
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], v0, v2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x7e00
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
+; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v4
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-GISEL-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v5, v4, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v2, v5, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_pk_max_f16 v4, v1, v3
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v6, v5, vcc
+; GFX9-GISEL-NEXT: v_pk_max_f16 v2, v1, v3
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc
+; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v4
+; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-SDAG-LABEL: test_fmaximum_v3f16_vv:
@@ -454,8 +518,11 @@ define amdgpu_ps <3 x half> @test_fmaximum_v3f16_vv(<3 x half> %a, <3 x half> %b
;
; GFX12-GISEL-FAKE16-LABEL: test_fmaximum_v3f16_vv:
; GFX12-GISEL-FAKE16: ; %bb.0:
-; GFX12-GISEL-FAKE16-NEXT: v_pk_maximum_f16 v0, v0, v2
; GFX12-GISEL-FAKE16-NEXT: v_maximum_f16 v1, v1, v3
+; GFX12-GISEL-FAKE16-NEXT: v_pk_maximum_f16 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX12-GISEL-FAKE16-NEXT: ; return to shader part epilog
%val = call <3 x half> @llvm.maximum.v3f16(<3 x half> %a, <3 x half> %b)
ret <3 x half> %val
@@ -490,19 +557,33 @@ define amdgpu_ps <3 x half> @test_fmaximum_v3f16_ss(<3 x half> inreg %a, <3 x ha
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT: s_lshr_b32 s4, s0, 16
; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s0, v0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s5
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7e00
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
-; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v2
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
-; GFX9-GISEL-NEXT: v_pk_max_f16 v3, s1, v1
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s1, v1
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v0
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX9-GISEL-NEXT: s_lshr_b32 s5, s2, 16
+; GFX9-GISEL-NEXT: s_and_b32 s0, s0, 1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, s2, 0x7e00
+; GFX9-GISEL-NEXT: s_and_b32 s2, s4, 1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s1, v0
+; GFX9-GISEL-NEXT: s_cselect_b32 s2, s5, 0x7e00
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s1, v0
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s1, s1, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, s3, 0x7e00
+; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-SDAG-LABEL: test_fmaximum_v3f16_ss:
@@ -607,27 +688,45 @@ define amdgpu_ps <4 x half> @test_fmaximum_v4f16_ss(<4 x half> inreg %a, <4 x ha
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT: s_lshr_b32 s2, s2, 16
; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s0, v0
-; GFX9-GISEL-NEXT: s_lshr_b32 s4, s0, 16
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7e00
+; GFX9-GISEL-NEXT: s_lshr_b32 s5, s0, 16
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
-; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v2
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-GISEL-NEXT: s_lshr_b32 s2, s3, 16
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-GISEL-NEXT: s_lshr_b32 s0, s1, 16
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s2
-; GFX9-GISEL-NEXT: v_pk_max_f16 v2, s1, v1
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v3
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], s1, v1
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, v2, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v2, v4, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s5, v0
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-GISEL-NEXT: s_lshr_b32 s5, s4, 16
+; GFX9-GISEL-NEXT: s_and_b32 s0, s0, 1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, s4, 0x7e00
+; GFX9-GISEL-NEXT: s_and_b32 s2, s2, 1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s2, s5, 0x7e00
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-GISEL-NEXT: s_lshr_b32 s3, s3, 16
+; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s1, v0
+; GFX9-GISEL-NEXT: s_lshr_b32 s4, s1, 16
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s1, v0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v0
+; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX9-GISEL-NEXT: s_lshr_b32 s4, s2, 16
+; GFX9-GISEL-NEXT: s_and_b32 s1, s1, 1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, s2, 0x7e00
+; GFX9-GISEL-NEXT: s_and_b32 s2, s3, 1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s2, s4, 0x7e00
+; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s1, s1, s2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fmaximum_v4f16_ss:
@@ -683,17 +782,36 @@ define amdgpu_ps <2 x float> @test_fmaximum_f64_ss(double inreg %a, double inreg
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[0:1], v[0:1]
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1]
+; GFX9-GISEL-NEXT: s_mov_b32 s2, 0
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0x7ff80000
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s4, s4, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX9-GISEL-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: test_fmaximum_f64_ss:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_maximum_f64 v[0:1], s[0:1], s[2:3]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-SDAG-LABEL: test_fmaximum_f64_ss:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: v_maximum_f64 v[0:1], s[0:1], s[2:3]
+; GFX12-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: test_fmaximum_f64_ss:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_maximum_f64 v[0:1], s[0:1], s[2:3]
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%val = call double @llvm.maximum.f64(double %a, double %b)
%ret = bitcast double %val to <2 x float>
ret <2 x float> %ret
@@ -721,24 +839,55 @@ define amdgpu_ps <4 x float> @test_fmaximum_v2f64_ss(<2 x double> inreg %a, <2 x
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s5
-; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[0:1], v[0:1]
+; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s7
-; GFX9-GISEL-NEXT: v_max_f64 v[4:5], s[2:3], v[0:1]
-; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], s[2:3], v[0:1]
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v6, v5, s[0:1]
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[2:3], v[0:1]
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[2:3], v[0:1]
+; GFX9-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX9-GISEL-NEXT: s_mov_b32 s2, 0
+; GFX9-GISEL-NEXT: s_and_b32 s4, s4, 1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0x7ff80000
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX9-GISEL-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s6, s6, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX9-GISEL-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: test_fmaximum_v2f64_ss:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_maximum_f64 v[0:1], s[0:1], s[4:5]
-; GFX12-NEXT: v_maximum_f64 v[2:3], s[2:3], s[6:7]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-SDAG-LABEL: test_fmaximum_v2f64_ss:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: v_maximum_f64 v[0:1], s[0:1], s[4:5]
+; GFX12-SDAG-NEXT: v_maximum_f64 v[2:3], s[2:3], s[6:7]
+; GFX12-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: test_fmaximum_v2f64_ss:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_maximum_f64 v[0:1], s[0:1], s[4:5]
+; GFX12-GISEL-NEXT: v_maximum_f64 v[2:3], s[2:3], s[6:7]
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%val = call <2 x double> @llvm.maximum.v2f64(<2 x double> %a, <2 x double> %b)
%ret = bitcast <2 x double> %val to <4 x float>
ret <4 x float> %ret
@@ -833,75 +982,167 @@ define amdgpu_ps <8 x float> @test_fmaximum_v4f64_ss(<4 x double> inreg %a, <4 x
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s8
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s9
-; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[0:1], v[0:1]
+; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s10
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s11
-; GFX9-GISEL-NEXT: v_max_f64 v[4:5], s[2:3], v[0:1]
-; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], s[2:3], v[0:1]
+; GFX9-GISEL-NEXT: s_mov_b32 s8, 0
+; GFX9-GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[2:3], v[0:1]
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[2:3], v[0:1]
+; GFX9-GISEL-NEXT: s_cselect_b32 s16, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s2, s16, 1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s12
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s13
-; GFX9-GISEL-NEXT: v_max_f64 v[6:7], s[4:5], v[0:1]
-; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[2:3], s[4:5], v[0:1]
+; GFX9-GISEL-NEXT: s_cselect_b64 s[2:3], s[0:1], s[8:9]
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[4:5], v[0:1]
+; GFX9-GISEL-NEXT: s_cselect_b32 s10, 1, 0
+; GFX9-GISEL-NEXT: v_max_f64 v[4:5], s[4:5], v[0:1]
+; GFX9-GISEL-NEXT: s_and_b32 s10, s10, 1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s14
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s10, 0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s15
-; GFX9-GISEL-NEXT: v_max_f64 v[8:9], s[6:7], v[0:1]
-; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[4:5], s[6:7], v[0:1]
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff80000
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v10, v5, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v10, v7, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v8, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v7, v10, v9, s[4:5]
+; GFX9-GISEL-NEXT: s_cselect_b64 s[4:5], s[0:1], s[8:9]
+; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], s[6:7], v[0:1]
+; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[6:7], v[0:1]
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s6, s6, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s10, v4
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s11, v5
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX9-GISEL-NEXT: s_cselect_b64 s[6:7], s[10:11], s[8:9]
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s0, s0, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s11, v3
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-GISEL-NEXT: s_cselect_b64 s[0:1], s[10:11], s[8:9]
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, s7
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, s0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v7, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: test_fmaximum_v4f64_ss:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_maximum_f64 v[0:1], s[0:1], s[8:9]
-; GFX12-NEXT: v_maximum_f64 v[2:3], s[2:3], s[10:11]
-; GFX12-NEXT: v_maximum_f64 v[4:5], s[4:5], s[12:13]
-; GFX12-NEXT: v_maximum_f64 v[6:7], s[6:7], s[14:15]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-SDAG-LABEL: test_fmaximum_v4f64_ss:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: v_maximum_f64 v[0:1], s[0:1], s[8:9]
+; GFX12-SDAG-NEXT: v_maximum_f64 v[2:3], s[2:3], s[10:11]
+; GFX12-SDAG-NEXT: v_maximum_f64 v[4:5], s[4:5], s[12:13]
+; GFX12-SDAG-NEXT: v_maximum_f64 v[6:7], s[6:7], s[14:15]
+; GFX12-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: test_fmaximum_v4f64_ss:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_maximum_f64 v[0:1], s[0:1], s[8:9]
+; GFX12-GISEL-NEXT: v_maximum_f64 v[2:3], s[2:3], s[10:11]
+; GFX12-GISEL-NEXT: v_maximum_f64 v[4:5], s[4:5], s[12:13]
+; GFX12-GISEL-NEXT: v_maximum_f64 v[6:7], s[6:7], s[14:15]
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v6
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v7
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%val = call <4 x double> @llvm.maximum.v4f64(<4 x double> %a, <4 x double> %b)
%ret = bitcast <4 x double> %val to <8 x float>
ret <8 x float> %ret
}
define amdgpu_kernel void @fmaximumi_f32_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
-; GFX9-LABEL: fmaximumi_f32_move_to_valu:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: global_load_dword v2, v0, s[6:7] glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_max_f32_e32 v4, v1, v2
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX9-NEXT: s_endpgm
+; GFX9-SDAG-LABEL: fmaximumi_f32_move_to_valu:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: global_load_dword v1, v0, s[2:3] glc
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX9-SDAG-NEXT: global_load_dword v2, v0, s[6:7] glc
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e32 v4, v1, v2
+; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, v1, v2
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX9-SDAG-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX9-SDAG-NEXT: s_endpgm
;
-; GFX12-LABEL: fmaximumi_f32_move_to_valu:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_clause 0x1
-; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_maximum_f32 v1, v1, v2
-; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX12-NEXT: s_endpgm
+; GFX9-GISEL-LABEL: fmaximumi_f32_move_to_valu:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: global_load_dword v1, v0, s[2:3] glc
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9-GISEL-NEXT: global_load_dword v2, v0, s[6:7] glc
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, v1, v2
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v1, v2
+; GFX9-GISEL-NEXT: s_and_b32 s3, s3, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v3
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s2, s2, 0x7fc00000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX9-GISEL-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: fmaximumi_f32_move_to_valu:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
+; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-NEXT: global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS
+; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-NEXT: v_maximum_f32 v1, v1, v2
+; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: fmaximumi_f32_move_to_valu:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; GFX12-GISEL-NEXT: s_maximum_f32 s2, s2, s3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-GISEL-NEXT: s_endpgm
%a = load volatile float, ptr addrspace(1) %aptr, align 4
%b = load volatile float, ptr addrspace(1) %bptr, align 4
%v = call float @llvm.maximum.f32(float %a, float %b)
@@ -910,22 +1151,47 @@ define amdgpu_kernel void @fmaximumi_f32_move_to_valu(ptr addrspace(1) %out, ptr
}
define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
-; GFX9-LABEL: fmaximum_f16_move_to_valu:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: global_load_ushort v2, v0, s[6:7] glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_max_f16_e32 v4, v1, v2
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX9-NEXT: global_store_short v0, v1, s[0:1]
-; GFX9-NEXT: s_endpgm
+; GFX9-SDAG-LABEL: fmaximum_f16_move_to_valu:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x7e00
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: global_load_ushort v1, v0, s[2:3] glc
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX9-SDAG-NEXT: global_load_ushort v2, v0, s[6:7] glc
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f16_e32 v4, v1, v2
+; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, v1, v2
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX9-SDAG-NEXT: global_store_short v0, v1, s[0:1]
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: fmaximum_f16_move_to_valu:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: global_load_ushort v1, v0, s[2:3] glc
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9-GISEL-NEXT: global_load_ushort v2, v0, s[6:7] glc
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s2, v1
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX9-GISEL-NEXT: v_max_f16_e32 v2, s2, v1
+; GFX9-GISEL-NEXT: s_and_b32 s3, s3, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s2, s2, 0x7e00
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX9-GISEL-NEXT: global_store_short v0, v1, s[0:1]
+; GFX9-GISEL-NEXT: s_endpgm
;
; GFX12-SDAG-TRUE16-LABEL: fmaximum_f16_move_to_valu:
; GFX12-SDAG-TRUE16: ; %bb.0:
@@ -966,9 +1232,13 @@ define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] scope:SCOPE_SYS
+; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v2, v1, s[4:5] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
+; GFX12-GISEL-TRUE16-NEXT: s_maximum_f16 s2, s2, s3
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-GISEL-TRUE16-NEXT: s_endpgm
;
@@ -983,7 +1253,11 @@ define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5] scope:SCOPE_SYS
; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-FAKE16-NEXT: v_maximum_f16 v1, v1, v2
+; GFX12-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s3, v2
+; GFX12-GISEL-FAKE16-NEXT: s_maximum_f16 s2, s2, s3
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, s2
; GFX12-GISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX12-GISEL-FAKE16-NEXT: s_endpgm
%a = load volatile half, ptr addrspace(1) %aptr, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll b/llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
index 7a89b58f239a9..9330841c97227 100644
--- a/llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
@@ -1,15 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test no legal f16. Should just keep the cast to f32 and
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-GISEL %s
; Test legal f16, no f16 fmed3. Should expand to min/max sequence
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
; Legal f16 med3. InstCombine ought to shrink the f32 op to f16 so the codegen doesn't really matter for this.
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
declare float @llvm.amdgcn.fmed3.f32(float, float, float) #0
diff --git a/llvm/test/CodeGen/AMDGPU/fmed3.ll b/llvm/test/CodeGen/AMDGPU/fmed3.ll
index 668347eb97004..f0b6b73218d28 100644
--- a/llvm/test/CodeGen/AMDGPU/fmed3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmed3.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=amdgcn -global-isel=0 < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-SDAG %s
-; RUN: llc -mtriple=amdgcn -global-isel=1 < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-GISEL %s
+; RUN: llc -mtriple=amdgcn -global-isel=1 -new-reg-bank-select < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=0 < %s | FileCheck -enable-var-scope -check-prefixes=VI-SDAG %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 < %s | FileCheck -enable-var-scope -check-prefixes=VI-GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -enable-var-scope -check-prefixes=VI-GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-SDAG %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
define amdgpu_kernel void @v_test_nnan_input_fmed3_r_i_i_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {
; SI-SDAG-LABEL: v_test_nnan_input_fmed3_r_i_i_f32:
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum.ll b/llvm/test/CodeGen/AMDGPU/fminimum.ll
index 4cccc768d3c50..e77e39a1ce1ff 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define amdgpu_ps float @test_fminimum_f32_vv(float %a, float %b) {
; GFX9-LABEL: test_fminimum_f32_vv:
@@ -24,14 +24,28 @@ define amdgpu_ps float @test_fminimum_f32_vv(float %a, float %b) {
}
define amdgpu_ps float @test_fminimum_f32_ss(float inreg %a, float inreg %b) {
-; GFX9-LABEL: test_fminimum_f32_ss:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v0, s1
-; GFX9-NEXT: v_min_f32_e32 v1, s0, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GFX9-NEXT: ; return to shader part epilog
+; GFX9-SDAG-LABEL: test_fminimum_f32_ss:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-SDAG-NEXT: v_min_f32_e32 v1, s0, v0
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX9-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX9-GISEL-LABEL: test_fminimum_f32_ss:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_min_f32_e32 v1, s0, v0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s0, s0, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, s1, 0x7fc00000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fminimum_f32_ss:
; GFX12: ; %bb.0:
@@ -127,18 +141,42 @@ define amdgpu_ps <2 x float> @test_fminimum_v2f32(<2 x float> %a, <2 x float> %b
}
define amdgpu_ps <2 x float> @test_fminimum_v2f32_ss(<2 x float> inreg %a, <2 x float> inreg %b) {
-; GFX9-LABEL: test_fminimum_v2f32_ss:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_min_f32_e32 v1, s0, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: v_min_f32_e32 v3, s1, v1
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s1, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; GFX9-NEXT: ; return to shader part epilog
+; GFX9-SDAG-LABEL: test_fminimum_v2f32_ss:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-SDAG-NEXT: v_min_f32_e32 v1, s0, v0
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-SDAG-NEXT: v_min_f32_e32 v3, s1, v1
+; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, s1, v1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; GFX9-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX9-GISEL-LABEL: test_fminimum_v2f32_ss:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, s0, v0
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_min_f32_e32 v1, s0, v0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s0, s0, 1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, s1, v0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, s2, 0x7fc00000
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_min_f32_e32 v1, s1, v0
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s1, s1, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, s2, 0x7fc00000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fminimum_v2f32_ss:
; GFX12: ; %bb.0:
@@ -315,14 +353,28 @@ define amdgpu_ps half @test_fminimum_f16_vv(half %a, half %b) {
}
define amdgpu_ps half @test_fminimum_f16_ss(half inreg %a, half inreg %b) {
-; GFX9-LABEL: test_fminimum_f16_ss:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v0, s1
-; GFX9-NEXT: v_min_f16_e32 v1, s0, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x7e00
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GFX9-NEXT: ; return to shader part epilog
+; GFX9-SDAG-LABEL: test_fminimum_f16_ss:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-SDAG-NEXT: v_min_f16_e32 v1, s0, v0
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7e00
+; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX9-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX9-GISEL-LABEL: test_fminimum_f16_ss:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_min_f16_e32 v1, s0, v0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s0, s0, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, s1, 0x7e00
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fminimum_f16_ss:
; GFX12: ; %bb.0:
@@ -389,16 +441,25 @@ define amdgpu_ps <2 x half> @test_fminimum_v2f16_ss(<2 x half> inreg %a, <2 x ha
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX9-GISEL-NEXT: s_lshr_b32 s1, s1, 16
-; GFX9-GISEL-NEXT: s_lshr_b32 s2, s0, 16
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s1
; GFX9-GISEL-NEXT: v_pk_min_f16 v1, s0, v0
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s2, v2
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x7e00
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], s0, v0
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-GISEL-NEXT: s_lshr_b32 s3, s0, 16
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s3, v0
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX9-GISEL-NEXT: s_lshr_b32 s3, s2, 16
+; GFX9-GISEL-NEXT: s_and_b32 s0, s0, 1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, s2, 0x7e00
+; GFX9-GISEL-NEXT: s_and_b32 s1, s1, 1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, s3, 0x7e00
+; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fminimum_v2f16_ss:
@@ -428,16 +489,19 @@ define amdgpu_ps <3 x half> @test_fminimum_v3f16_vv(<3 x half> %a, <3 x half> %b
; GFX9-GISEL-LABEL: test_fminimum_v3f16_vv:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_pk_min_f16 v4, v0, v2
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x7e00
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], v0, v2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x7e00
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
+; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v4
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-GISEL-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v5, v4, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v2, v5, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_pk_min_f16 v4, v1, v3
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v6, v5, vcc
+; GFX9-GISEL-NEXT: v_pk_min_f16 v2, v1, v3
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc
+; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v4
+; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-SDAG-LABEL: test_fminimum_v3f16_vv:
@@ -454,8 +518,11 @@ define amdgpu_ps <3 x half> @test_fminimum_v3f16_vv(<3 x half> %a, <3 x half> %b
;
; GFX12-GISEL-FAKE16-LABEL: test_fminimum_v3f16_vv:
; GFX12-GISEL-FAKE16: ; %bb.0:
-; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v2
; GFX12-GISEL-FAKE16-NEXT: v_minimum_f16 v1, v1, v3
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX12-GISEL-FAKE16-NEXT: ; return to shader part epilog
%val = call <3 x half> @llvm.minimum.v3f16(<3 x half> %a, <3 x half> %b)
ret <3 x half> %val
@@ -490,19 +557,33 @@ define amdgpu_ps <3 x half> @test_fminimum_v3f16_ss(<3 x half> inreg %a, <3 x ha
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT: s_lshr_b32 s4, s0, 16
; GFX9-GISEL-NEXT: v_pk_min_f16 v1, s0, v0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s5
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7e00
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
-; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v2
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
-; GFX9-GISEL-NEXT: v_pk_min_f16 v3, s1, v1
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s1, v1
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v0
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX9-GISEL-NEXT: s_lshr_b32 s5, s2, 16
+; GFX9-GISEL-NEXT: s_and_b32 s0, s0, 1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, s2, 0x7e00
+; GFX9-GISEL-NEXT: s_and_b32 s2, s4, 1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s1, v0
+; GFX9-GISEL-NEXT: s_cselect_b32 s2, s5, 0x7e00
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_pk_min_f16 v1, s1, v0
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s1, s1, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, s3, 0x7e00
+; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-SDAG-LABEL: test_fminimum_v3f16_ss:
@@ -607,27 +688,45 @@ define amdgpu_ps <4 x half> @test_fminimum_v4f16_ss(<4 x half> inreg %a, <4 x ha
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT: s_lshr_b32 s2, s2, 16
; GFX9-GISEL-NEXT: v_pk_min_f16 v1, s0, v0
-; GFX9-GISEL-NEXT: s_lshr_b32 s4, s0, 16
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7e00
+; GFX9-GISEL-NEXT: s_lshr_b32 s5, s0, 16
; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0
-; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v2
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-GISEL-NEXT: s_lshr_b32 s2, s3, 16
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-GISEL-NEXT: s_lshr_b32 s0, s1, 16
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s2
-; GFX9-GISEL-NEXT: v_pk_min_f16 v2, s1, v1
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v3
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], s1, v1
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, v2, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v2, v4, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s5, v0
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-GISEL-NEXT: s_lshr_b32 s5, s4, 16
+; GFX9-GISEL-NEXT: s_and_b32 s0, s0, 1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, s4, 0x7e00
+; GFX9-GISEL-NEXT: s_and_b32 s2, s2, 1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s2, s5, 0x7e00
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-GISEL-NEXT: s_lshr_b32 s3, s3, 16
+; GFX9-GISEL-NEXT: v_pk_min_f16 v1, s1, v0
+; GFX9-GISEL-NEXT: s_lshr_b32 s4, s1, 16
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s1, v0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v0
+; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX9-GISEL-NEXT: s_lshr_b32 s4, s2, 16
+; GFX9-GISEL-NEXT: s_and_b32 s1, s1, 1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s1, s2, 0x7e00
+; GFX9-GISEL-NEXT: s_and_b32 s2, s3, 1
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s2, s4, 0x7e00
+; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s1, s1, s2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_fminimum_v4f16_ss:
@@ -683,17 +782,36 @@ define amdgpu_ps <2 x float> @test_fminimum_f64_ss(double inreg %a, double inreg
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-GISEL-NEXT: v_min_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[0:1], v[0:1]
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-GISEL-NEXT: v_min_f64 v[2:3], s[0:1], v[0:1]
+; GFX9-GISEL-NEXT: s_mov_b32 s2, 0
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0x7ff80000
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s4, s4, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX9-GISEL-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: test_fminimum_f64_ss:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_minimum_f64 v[0:1], s[0:1], s[2:3]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-SDAG-LABEL: test_fminimum_f64_ss:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], s[0:1], s[2:3]
+; GFX12-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: test_fminimum_f64_ss:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], s[0:1], s[2:3]
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%val = call double @llvm.minimum.f64(double %a, double %b)
%ret = bitcast double %val to <2 x float>
ret <2 x float> %ret
@@ -721,24 +839,55 @@ define amdgpu_ps <4 x float> @test_fminimum_v2f64_ss(<2 x double> inreg %a, <2 x
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s5
-; GFX9-GISEL-NEXT: v_min_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[0:1], v[0:1]
+; GFX9-GISEL-NEXT: v_min_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s7
-; GFX9-GISEL-NEXT: v_min_f64 v[4:5], s[2:3], v[0:1]
-; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], s[2:3], v[0:1]
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v6, v5, s[0:1]
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[2:3], v[0:1]
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX9-GISEL-NEXT: v_min_f64 v[2:3], s[2:3], v[0:1]
+; GFX9-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX9-GISEL-NEXT: s_mov_b32 s2, 0
+; GFX9-GISEL-NEXT: s_and_b32 s4, s4, 1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0x7ff80000
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX9-GISEL-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s6, s6, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX9-GISEL-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: test_fminimum_v2f64_ss:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_minimum_f64 v[0:1], s[0:1], s[4:5]
-; GFX12-NEXT: v_minimum_f64 v[2:3], s[2:3], s[6:7]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-SDAG-LABEL: test_fminimum_v2f64_ss:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], s[0:1], s[4:5]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[2:3], s[2:3], s[6:7]
+; GFX12-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: test_fminimum_v2f64_ss:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], s[0:1], s[4:5]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], s[2:3], s[6:7]
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%val = call <2 x double> @llvm.minimum.v2f64(<2 x double> %a, <2 x double> %b)
%ret = bitcast <2 x double> %val to <4 x float>
ret <4 x float> %ret
@@ -833,75 +982,167 @@ define amdgpu_ps <8 x float> @test_fminimum_v4f64_ss(<4 x double> inreg %a, <4 x
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s8
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s9
-; GFX9-GISEL-NEXT: v_min_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[0:1], v[0:1]
+; GFX9-GISEL-NEXT: v_min_f64 v[2:3], s[0:1], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s10
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s11
-; GFX9-GISEL-NEXT: v_min_f64 v[4:5], s[2:3], v[0:1]
-; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], s[2:3], v[0:1]
+; GFX9-GISEL-NEXT: s_mov_b32 s8, 0
+; GFX9-GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[2:3], v[0:1]
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX9-GISEL-NEXT: v_min_f64 v[2:3], s[2:3], v[0:1]
+; GFX9-GISEL-NEXT: s_cselect_b32 s16, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s2, s16, 1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s12
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s13
-; GFX9-GISEL-NEXT: v_min_f64 v[6:7], s[4:5], v[0:1]
-; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[2:3], s[4:5], v[0:1]
+; GFX9-GISEL-NEXT: s_cselect_b64 s[2:3], s[0:1], s[8:9]
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[4:5], v[0:1]
+; GFX9-GISEL-NEXT: s_cselect_b32 s10, 1, 0
+; GFX9-GISEL-NEXT: v_min_f64 v[4:5], s[4:5], v[0:1]
+; GFX9-GISEL-NEXT: s_and_b32 s10, s10, 1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s14
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s10, 0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s15
-; GFX9-GISEL-NEXT: v_min_f64 v[8:9], s[6:7], v[0:1]
-; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[4:5], s[6:7], v[0:1]
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff80000
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v10, v5, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v10, v7, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v8, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v7, v10, v9, s[4:5]
+; GFX9-GISEL-NEXT: s_cselect_b64 s[4:5], s[0:1], s[8:9]
+; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], s[6:7], v[0:1]
+; GFX9-GISEL-NEXT: v_min_f64 v[2:3], s[6:7], v[0:1]
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s6, s6, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s10, v4
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s11, v5
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX9-GISEL-NEXT: s_cselect_b64 s[6:7], s[10:11], s[8:9]
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-GISEL-NEXT: s_and_b32 s0, s0, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s11, v3
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-GISEL-NEXT: s_cselect_b64 s[0:1], s[10:11], s[8:9]
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, s7
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, s0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v7, s1
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: test_fminimum_v4f64_ss:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_minimum_f64 v[0:1], s[0:1], s[8:9]
-; GFX12-NEXT: v_minimum_f64 v[2:3], s[2:3], s[10:11]
-; GFX12-NEXT: v_minimum_f64 v[4:5], s[4:5], s[12:13]
-; GFX12-NEXT: v_minimum_f64 v[6:7], s[6:7], s[14:15]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-SDAG-LABEL: test_fminimum_v4f64_ss:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], s[0:1], s[8:9]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[2:3], s[2:3], s[10:11]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[4:5], s[4:5], s[12:13]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[6:7], s[6:7], s[14:15]
+; GFX12-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: test_fminimum_v4f64_ss:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], s[0:1], s[8:9]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], s[2:3], s[10:11]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[4:5], s[4:5], s[12:13]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[6:7], s[6:7], s[14:15]
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v6
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v7
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%val = call <4 x double> @llvm.minimum.v4f64(<4 x double> %a, <4 x double> %b)
%ret = bitcast <4 x double> %val to <8 x float>
ret <8 x float> %ret
}
define amdgpu_kernel void @fminimumi_f32_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
-; GFX9-LABEL: fminimumi_f32_move_to_valu:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: global_load_dword v2, v0, s[6:7] glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_min_f32_e32 v4, v1, v2
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX9-NEXT: s_endpgm
+; GFX9-SDAG-LABEL: fminimumi_f32_move_to_valu:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: global_load_dword v1, v0, s[2:3] glc
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX9-SDAG-NEXT: global_load_dword v2, v0, s[6:7] glc
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX9-SDAG-NEXT: v_min_f32_e32 v4, v1, v2
+; GFX9-SDAG-NEXT: v_cmp_o_f32_e32 vcc, v1, v2
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX9-SDAG-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX9-SDAG-NEXT: s_endpgm
;
-; GFX12-LABEL: fminimumi_f32_move_to_valu:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_clause 0x1
-; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_minimum_f32 v1, v1, v2
-; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX12-NEXT: s_endpgm
+; GFX9-GISEL-LABEL: fminimumi_f32_move_to_valu:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: global_load_dword v1, v0, s[2:3] glc
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9-GISEL-NEXT: global_load_dword v2, v0, s[6:7] glc
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9-GISEL-NEXT: v_cmp_o_f32_e32 vcc, v1, v2
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX9-GISEL-NEXT: v_min_f32_e32 v3, v1, v2
+; GFX9-GISEL-NEXT: s_and_b32 s3, s3, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v3
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s2, s2, 0x7fc00000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX9-GISEL-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: fminimumi_f32_move_to_valu:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
+; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-NEXT: global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS
+; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-NEXT: v_minimum_f32 v1, v1, v2
+; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: fminimumi_f32_move_to_valu:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; GFX12-GISEL-NEXT: s_minimum_f32 s2, s2, s3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-GISEL-NEXT: s_endpgm
%a = load volatile float, ptr addrspace(1) %aptr, align 4
%b = load volatile float, ptr addrspace(1) %bptr, align 4
%v = call float @llvm.minimum.f32(float %a, float %b)
@@ -910,22 +1151,47 @@ define amdgpu_kernel void @fminimumi_f32_move_to_valu(ptr addrspace(1) %out, ptr
}
define amdgpu_kernel void @fminimum_f16_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
-; GFX9-LABEL: fminimum_f16_move_to_valu:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: global_load_ushort v2, v0, s[6:7] glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_min_f16_e32 v4, v1, v2
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX9-NEXT: global_store_short v0, v1, s[0:1]
-; GFX9-NEXT: s_endpgm
+; GFX9-SDAG-LABEL: fminimum_f16_move_to_valu:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x7e00
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: global_load_ushort v1, v0, s[2:3] glc
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX9-SDAG-NEXT: global_load_ushort v2, v0, s[6:7] glc
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX9-SDAG-NEXT: v_min_f16_e32 v4, v1, v2
+; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, v1, v2
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX9-SDAG-NEXT: global_store_short v0, v1, s[0:1]
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: fminimum_f16_move_to_valu:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: global_load_ushort v1, v0, s[2:3] glc
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9-GISEL-NEXT: global_load_ushort v2, v0, s[6:7] glc
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s2, v1
+; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX9-GISEL-NEXT: v_min_f16_e32 v2, s2, v1
+; GFX9-GISEL-NEXT: s_and_b32 s3, s3, 1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s2, s2, 0x7e00
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX9-GISEL-NEXT: global_store_short v0, v1, s[0:1]
+; GFX9-GISEL-NEXT: s_endpgm
;
; GFX12-SDAG-TRUE16-LABEL: fminimum_f16_move_to_valu:
; GFX12-SDAG-TRUE16: ; %bb.0:
@@ -966,9 +1232,13 @@ define amdgpu_kernel void @fminimum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] scope:SCOPE_SYS
+; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v2, v1, s[4:5] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
+; GFX12-GISEL-TRUE16-NEXT: s_minimum_f16 s2, s2, s3
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-GISEL-TRUE16-NEXT: s_endpgm
;
@@ -983,7 +1253,11 @@ define amdgpu_kernel void @fminimum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5] scope:SCOPE_SYS
; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-FAKE16-NEXT: v_minimum_f16 v1, v1, v2
+; GFX12-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s3, v2
+; GFX12-GISEL-FAKE16-NEXT: s_minimum_f16 s2, s2, s3
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, s2
; GFX12-GISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX12-GISEL-FAKE16-NEXT: s_endpgm
%a = load volatile half, ptr addrspace(1) %aptr, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
index 62c62c9159bac..e174d75122097 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
@@ -1,5 +1,5 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -start-before=amdgpu-unify-divergent-exit-nodes < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-SDAG %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -start-before=amdgpu-unify-divergent-exit-nodes < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-GISEL %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -start-before=amdgpu-unify-divergent-exit-nodes < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-GISEL %s
; --------------------------------------------------------------------------------
; fminimum tests
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
index 7044afb09e371..1aaa5572e77e9 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
@@ -6,11 +6,11 @@
; RUN: llc -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=SDAG-CI %s
; FIXME-TRUE16. fix gisel
-; XUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-FAKE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GISEL-GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=GISEL-CI %s
+; XUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-FAKE16 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GISEL-GFX9 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=GISEL-CI %s
define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo(half %src0, half %src1, half %src2) #0 {
; GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:
@@ -414,12 +414,12 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %
; SDAG-GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GFX9-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
+; SDAG-GFX9: ; %bb.0:
+; SDAG-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; SDAG-GFX9-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
; VI: ; %bb.0:
@@ -446,11 +446,22 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %
; GISEL-GFX11: ; %bb.0:
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX11-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-NEXT: v_and_b32_e64 v1, 0xffff, s0
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GISEL-GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
+; GISEL-GFX9: ; %bb.0:
+; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0xffff
+; GISEL-GFX9-NEXT: v_and_b32_e32 v1, s4, v1
+; GISEL-GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
index 154d6c7079672..bacdf308c7df1 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
@@ -7,12 +7,12 @@
; RUN: llc -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=SDAG-CI %s
; FIXME-TRUE16. enable gisel
-; XUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-FAKE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX900,GISEL-GFX900 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX906,GISEL-GFX906 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=GISEL-CI %s
+; XUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-FAKE16 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX900,GISEL-GFX900 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX906,GISEL-GFX906 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=GISEL-CI %s
define half @mixlo_simple(float %src0, float %src1, float %src2) #0 {
; GFX1100-LABEL: mixlo_simple:
@@ -627,19 +627,23 @@ define <3 x half> @v_mad_mix_v3f32(<3 x half> %src0, <3 x half> %src1, <3 x half
; GISEL-GFX1100-LABEL: v_mad_mix_v3f32:
; GISEL-GFX1100: ; %bb.0:
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v6
+; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_and_b32 v1, 0xffff, v1
+; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v3f32:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX900-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
-; GISEL-GFX900-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; GISEL-GFX900-NEXT: v_mad_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX900-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX900-NEXT: v_and_b32_e32 v0, 0xffff, v1
+; GISEL-GFX900-NEXT: v_lshl_or_b32 v1, s4, 16, v0
; GISEL-GFX900-NEXT: v_mov_b32_e32 v0, v6
; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -647,8 +651,10 @@ define <3 x half> @v_mad_mix_v3f32(<3 x half> %src0, <3 x half> %src1, <3 x half
; GISEL-GFX906: ; %bb.0:
; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX906-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
-; GISEL-GFX906-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; GISEL-GFX906-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX906-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v1
+; GISEL-GFX906-NEXT: v_lshl_or_b32 v1, s4, 16, v0
; GISEL-GFX906-NEXT: v_mov_b32_e32 v0, v6
; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
;
@@ -1192,20 +1198,23 @@ define <3 x half> @v_mad_mix_v3f32_clamp_postcvt(<3 x half> %src0, <3 x half> %s
; GISEL-GFX1100-LABEL: v_mad_mix_v3f32_clamp_postcvt:
; GISEL-GFX1100: ; %bb.0:
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_and_b32 v1, 0xffff, v1
+; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GISEL-GFX1100-NEXT: v_pk_max_f16 v1, v1, v1 clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v6
; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v3f32_clamp_postcvt:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX900-NEXT: v_mad_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX900-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GISEL-GFX900-NEXT: v_mad_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX900-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GISEL-GFX900-NEXT: v_mad_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX900-NEXT: v_pk_max_f16 v1, v1, v1 clamp
; GISEL-GFX900-NEXT: v_mov_b32_e32 v0, v3
@@ -1215,7 +1224,9 @@ define <3 x half> @v_mad_mix_v3f32_clamp_postcvt(<3 x half> %src0, <3 x half> %s
; GISEL-GFX906: ; %bb.0:
; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX906-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX906-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GISEL-GFX906-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX906-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GISEL-GFX906-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX906-NEXT: v_pk_max_f16 v1, v1, v1 clamp
; GISEL-GFX906-NEXT: v_mov_b32_e32 v0, v3
@@ -2148,15 +2159,18 @@ define <3 x half> @v_mad_mix_v3f32_clamp_precvt(<3 x half> %src0, <3 x half> %sr
; GISEL-GFX1100-LABEL: v_mad_mix_v3f32_clamp_precvt:
; GISEL-GFX1100: ; %bb.0:
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v2, v6
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v2, v3
+; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GISEL-GFX1100-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GISEL-GFX1100-NEXT: v_pack_b32_f16 v0, v2, v0
+; GISEL-GFX1100-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v3f32_clamp_precvt:
@@ -2164,11 +2178,12 @@ define <3 x half> @v_mad_mix_v3f32_clamp_precvt(<3 x half> %src0, <3 x half> %sr
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX900-NEXT: v_mad_mix_f32 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
; GISEL-GFX900-NEXT: v_mad_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX900-NEXT: v_mad_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
; GISEL-GFX900-NEXT: v_cvt_f16_f32_e32 v2, v6
; GISEL-GFX900-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX900-NEXT: v_mad_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
; GISEL-GFX900-NEXT: v_cvt_f16_f32_e32 v1, v1
; GISEL-GFX900-NEXT: v_pack_b32_f16 v0, v2, v0
+; GISEL-GFX900-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX906-LABEL: v_mad_mix_v3f32_clamp_precvt:
@@ -2176,11 +2191,12 @@ define <3 x half> @v_mad_mix_v3f32_clamp_precvt(<3 x half> %src0, <3 x half> %sr
; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX906-NEXT: v_fma_mix_f32 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX906-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
; GISEL-GFX906-NEXT: v_cvt_f16_f32_e32 v2, v6
; GISEL-GFX906-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX906-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
; GISEL-GFX906-NEXT: v_cvt_f16_f32_e32 v1, v1
; GISEL-GFX906-NEXT: v_pack_b32_f16 v0, v2, v0
+; GISEL-GFX906-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-VI-LABEL: v_mad_mix_v3f32_clamp_precvt:
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix.ll b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
index fcd9dae983cfb..764907d2ad5a8 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
@@ -8,13 +8,13 @@
; RUN: llc -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CI,SDAG-CI %s
; FIXME-TRUE16. enable gisel
-; XUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-FAKE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX900,GISEL-GFX900 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX906,GISEL-GFX906 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx9-generic --amdhsa-code-object-version=6 < %s | FileCheck -check-prefixes=GFX9GEN,GISEL-GFX9GEN %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CI,GISEL-CI %s
+; XUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-FAKE16 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX900,GISEL-GFX900 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX906,GISEL-GFX906 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx9-generic --amdhsa-code-object-version=6 < %s | FileCheck -check-prefixes=GFX9GEN,GISEL-GFX9GEN %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CI,GISEL-CI %s
define float @v_mad_mix_f32_f16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo:
diff --git a/llvm/test/CodeGen/AMDGPU/minimummaximum.ll b/llvm/test/CodeGen/AMDGPU/minimummaximum.ll
index 4f33b6367c5fe..c246b9d97e75d 100644
--- a/llvm/test/CodeGen/AMDGPU/minimummaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimummaximum.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-FAKE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-FAKE16 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-TRUE16 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-FAKE16 %s
define amdgpu_ps float @test_minmax_f32(float %a, float %b, float %c) {
; GFX12-LABEL: test_minmax_f32:
diff --git a/llvm/test/CodeGen/AMDGPU/minmax.ll b/llvm/test/CodeGen/AMDGPU/minmax.ll
index dacee9a0173c5..456db08bda06b 100644
--- a/llvm/test/CodeGen/AMDGPU/minmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/minmax.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,SDAG,SDAG-GFX11,SDAG-GFX11-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,SDAG,SDAG-GFX11,SDAG-GFX11-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11,GISEL-GFX11-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11,GISEL-GFX11-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-GFX12,SDAG-GFX12-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-GFX12,SDAG-GFX12-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12,GISEL-GFX12-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12,GISEL-GFX12-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12,GISEL-GFX12-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12,GISEL-GFX12-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,SDAG,SDAG-GFX1250,SDAG-GFX1250-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,SDAG,SDAG-GFX1250,SDAG-GFX1250-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,GISEL,GISEL-GFX1250,GISEL-GFX1250-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,GISEL,GISEL-GFX1250,GISEL-GFX1250-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,GISEL,GISEL-GFX1250,GISEL-GFX1250-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,GISEL,GISEL-GFX1250,GISEL-GFX1250-FAKE16 %s
define i32 @test_minmax_i32(i32 %a, i32 %b, i32 %c) {
; GFX11-LABEL: test_minmax_i32:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
index 44b8b8bcb9ae8..f1d1ddf49bbff 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
@@ -1,20 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_fmax_v2half:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
index ed5c910def3d6..9b26912e659e6 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
@@ -1,20 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_fmin_v2half:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
index 63e42e1e8a320..deeac90a952c5 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
@@ -7,8 +7,8 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define half @test_vector_reduce_fminimum_v2half(<2 x half> %v) {
; GFX7-LABEL: test_vector_reduce_fminimum_v2half:
>From 04dbb9e9ed8d605248dbb5173c1acf6c771ee0cb Mon Sep 17 00:00:00 2001
From: Vang Thao <vang.thao at amd.com>
Date: Mon, 16 Feb 2026 20:52:00 -0800
Subject: [PATCH 2/2] Use HasIEEEMinMax predicate and update fmaxnum/fminnum.ll
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 15 +-
llvm/test/CodeGen/AMDGPU/fmaxnum.ll | 2701 ++++++++++++++++-
llvm/test/CodeGen/AMDGPU/fminnum.ll | 2613 +++++++++++++++-
3 files changed, 5126 insertions(+), 203 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index cfe653428228f..4a70ab2a902cf 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1229,8 +1229,19 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}});
- addRulesForGOpcs({G_FMINIMUM, G_FMAXIMUM, G_FMINNUM_IEEE, G_FMAXNUM_IEEE,
- G_FMINNUM, G_FMAXNUM},
+ bool HasIEEEMinMax = ST->hasIEEEMinimumMaximumInsts();
+
+ addRulesForGOpcs({G_FMINIMUM, G_FMAXIMUM}, Standard)
+ .Uni(S16, {{Sgpr16}, {Sgpr16, Sgpr16}})
+ .Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}})
+ .Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}}, HasIEEEMinMax)
+ .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}}, HasIEEEMinMax)
+ .Uni(S64, {{UniInVgprS64}, {Vgpr64, Vgpr64}}, HasIEEEMinMax)
+ .Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}}, HasIEEEMinMax)
+ .Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16}}, HasIEEEMinMax)
+ .Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}}, HasIEEEMinMax);
+
+ addRulesForGOpcs({G_FMINNUM_IEEE, G_FMAXNUM_IEEE, G_FMINNUM, G_FMAXNUM},
Standard)
.Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
diff --git a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
index be9027bdef823..d2db41b50e853 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
@@ -1,222 +1,2725 @@
-; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
-
-; GCN-LABEL: {{^}}test_fmax_f32_ieee_mode_on:
-; GCN: v_mul_f32_e64 [[QUIET0:v[0-9]+]], 1.0, s{{[0-9]+}}
-; GCN: v_mul_f32_e64 [[QUIET1:v[0-9]+]], 1.0, s{{[0-9]+}}
-; GCN: v_max_f32_e32 [[RESULT:v[0-9]+]], [[QUIET1]], [[QUIET0]]
-; GCN-NOT: [[RESULT]]
-; GCN: buffer_store_dword [[RESULT]]
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX8,GFX8-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX8,GFX8-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx908 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx908 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL %s
+
define amdgpu_kernel void @test_fmax_f32_ieee_mode_on(ptr addrspace(1) %out, float %a, float %b) #0 {
+; GFX8-SDAG-LABEL: test_fmax_f32_ieee_mode_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: s_mov_b64 s[4:5], s[2:3]
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s5
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s4
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_max_f32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmax_f32_ieee_mode_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, s2
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v1, 1.0, s3
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmax_f32_ieee_mode_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s3, s3
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s2, s2
+; GFX9-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX9-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX9-SDAG-NEXT: v_max_f32_e32 v0, v1, v0
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmax_f32_ieee_mode_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e64 v0, s2, s2
+; GFX9-GISEL-NEXT: v_max_f32_e64 v1, s3, s3
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmax_f32_ieee_mode_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s2, s2
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmax_f32_ieee_mode_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s2, s2
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s3, s3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: s_max_num_f32 s2, s2, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.maxnum.f32(float %a, float %b) #1
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}test_fmax_f32_ieee_mode_off:
-; GCN: v_max_f32_e32 v0, v0, v1
-; GCN-NEXT: ; return
define amdgpu_ps float @test_fmax_f32_ieee_mode_off(float %a, float %b) #0 {
+; GFX8-LABEL: test_fmax_f32_ieee_mode_off:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmax_f32_ieee_mode_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmax_f32_ieee_mode_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: ; return to shader part epilog
%val = call float @llvm.maxnum.f32(float %a, float %b) #1
ret float %val
}
-; GCN-LABEL: {{^}}test_fmax_v2f32:
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
define amdgpu_kernel void @test_fmax_v2f32(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b) #0 {
+; GFX8-SDAG-LABEL: test_fmax_v2f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s3
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s1
+; GFX8-SDAG-NEXT: v_max_f32_e32 v1, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s2
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v2, 1.0, s0
+; GFX8-SDAG-NEXT: v_max_f32_e32 v0, v2, v0
+; GFX8-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmax_v2f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_mov_b32 s6, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, s0
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v1, 1.0, s2
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s1
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s3
+; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
+; GFX8-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmax_v2f32:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s11, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s10, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s3, s3
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s1, s1
+; GFX9-SDAG-NEXT: v_max_f32_e32 v1, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s2, s2
+; GFX9-SDAG-NEXT: v_max_f32_e64 v2, s0, s0
+; GFX9-SDAG-NEXT: v_max_f32_e32 v0, v2, v0
+; GFX9-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmax_v2f32:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_mov_b32 s10, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s11, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e64 v0, s0, s0
+; GFX9-GISEL-NEXT: v_max_f32_e64 v1, s2, s2
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s1, s1
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s3, s3
+; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
+; GFX9-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmax_v2f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX12-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_mov_b32 s7, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s1, s1
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s2, s2
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v3, s0, s0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v0 :: v_dual_max_num_f32 v0, v3, v2
+; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmax_v2f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_mov_b32 s6, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s7, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s0, s0
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s2, s2
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s1, s1
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s3, s3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX12-GISEL-NEXT: s_max_num_f32 s0, s0, s1
+; GFX12-GISEL-NEXT: s_max_num_f32 s1, s2, s3
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b)
store <2 x float> %val, ptr addrspace(1) %out, align 8
ret void
}
-; GCN-LABEL: {{^}}test_fmax_v3f32:
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN-NOT: v_max_f32
define amdgpu_kernel void @test_fmax_v3f32(ptr addrspace(1) %out, <3 x float> %a, <3 x float> %b) nounwind {
+; GFX8-SDAG-LABEL: test_fmax_v3f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s14
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s10
+; GFX8-SDAG-NEXT: v_max_f32_e32 v2, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s13
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s9
+; GFX8-SDAG-NEXT: v_max_f32_e32 v1, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s12
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v3, 1.0, s8
+; GFX8-SDAG-NEXT: v_max_f32_e32 v0, v3, v0
+; GFX8-SDAG-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmax_v3f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, s8
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v1, 1.0, s12
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s9
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s13
+; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s10
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s14
+; GFX8-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX8-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmax_v3f32:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s14, s14
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s10, s10
+; GFX9-SDAG-NEXT: v_max_f32_e32 v2, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s13, s13
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s9, s9
+; GFX9-SDAG-NEXT: v_max_f32_e32 v1, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s12, s12
+; GFX9-SDAG-NEXT: v_max_f32_e64 v3, s8, s8
+; GFX9-SDAG-NEXT: v_max_f32_e32 v0, v3, v0
+; GFX9-SDAG-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmax_v3f32:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e64 v0, s8, s8
+; GFX9-GISEL-NEXT: v_max_f32_e64 v1, s12, s12
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s9, s9
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s13, s13
+; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s10, s10
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s14, s14
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmax_v3f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s14, s14
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s10, s10
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v3, s13, s13
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s9, s9
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s12, s12
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s8, s8
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v2, v1, v0 :: v_dual_max_num_f32 v1, v4, v3
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v6, v5
+; GFX12-SDAG-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmax_v3f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s8, s8
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s12, s12
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s9, s9
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s13, s13
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s10, s10
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v5, s14, s14
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v4
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s8, v5
+; GFX12-GISEL-NEXT: s_max_num_f32 s4, s2, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_max_num_f32 s5, s5, s6
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_max_num_f32 s6, s7, s8
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_2)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX12-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call <3 x float> @llvm.maxnum.v3f32(<3 x float> %a, <3 x float> %b)
store <3 x float> %val, ptr addrspace(1) %out, align 16
ret void
}
-; GCN-LABEL: {{^}}test_fmax_v4f32:
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
define amdgpu_kernel void @test_fmax_v4f32(ptr addrspace(1) %out, <4 x float> %a, <4 x float> %b) #0 {
+; GFX8-SDAG-LABEL: test_fmax_v4f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s15
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s11
+; GFX8-SDAG-NEXT: v_max_f32_e32 v3, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s14
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s10
+; GFX8-SDAG-NEXT: v_max_f32_e32 v2, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s13
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s9
+; GFX8-SDAG-NEXT: v_max_f32_e32 v1, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s12
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s8
+; GFX8-SDAG-NEXT: v_max_f32_e32 v0, v4, v0
+; GFX8-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmax_v4f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, s8
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v1, 1.0, s12
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s9
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s13
+; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s10
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s14
+; GFX8-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s11
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v4, 1.0, s15
+; GFX8-GISEL-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX8-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmax_v4f32:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s15, s15
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s11, s11
+; GFX9-SDAG-NEXT: v_max_f32_e32 v3, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s14, s14
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s10, s10
+; GFX9-SDAG-NEXT: v_max_f32_e32 v2, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s13, s13
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s9, s9
+; GFX9-SDAG-NEXT: v_max_f32_e32 v1, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s12, s12
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s8, s8
+; GFX9-SDAG-NEXT: v_max_f32_e32 v0, v4, v0
+; GFX9-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmax_v4f32:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e64 v0, s8, s8
+; GFX9-GISEL-NEXT: v_max_f32_e64 v1, s12, s12
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s9, s9
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s13, s13
+; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s10, s10
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s14, s14
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s11, s11
+; GFX9-GISEL-NEXT: v_max_f32_e64 v4, s15, s15
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX9-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmax_v4f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s15, s15
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s14, s14
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s13, s13
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s12, s12
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s8, s8
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v1, v0 :: v_dual_max_num_f32 v2, v4, v2
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v6, v5 :: v_dual_max_num_f32 v0, v8, v7
+; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmax_v4f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s8, s8
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s12, s12
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s9, s9
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s13, s13
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s10, s10
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v5, s14, s14
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v6, s11, s11
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v7, s15, s15
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v4
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s8, v5
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s9, v6
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s10, v7
+; GFX12-GISEL-NEXT: s_max_num_f32 s4, s2, s3
+; GFX12-GISEL-NEXT: s_max_num_f32 s5, s5, s6
+; GFX12-GISEL-NEXT: s_max_num_f32 s6, s7, s8
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_max_num_f32 s7, s9, s10
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b)
store <4 x float> %val, ptr addrspace(1) %out, align 16
ret void
}
-; GCN-LABEL: {{^}}test_fmax_v8f32:
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
define amdgpu_kernel void @test_fmax_v8f32(ptr addrspace(1) %out, <8 x float> %a, <8 x float> %b) #0 {
+; GFX8-SDAG-LABEL: test_fmax_v8f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x44
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s19
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s11
+; GFX8-SDAG-NEXT: v_max_f32_e32 v3, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s18
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s10
+; GFX8-SDAG-NEXT: v_max_f32_e32 v2, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s17
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s9
+; GFX8-SDAG-NEXT: v_max_f32_e32 v1, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s16
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s8
+; GFX8-SDAG-NEXT: v_max_f32_e32 v0, v4, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s23
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v5, 1.0, s15
+; GFX8-SDAG-NEXT: v_max_f32_e32 v7, v5, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s22
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v5, 1.0, s14
+; GFX8-SDAG-NEXT: v_max_f32_e32 v6, v5, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s21
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v5, 1.0, s13
+; GFX8-SDAG-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s20
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v8, 1.0, s12
+; GFX8-SDAG-NEXT: v_max_f32_e32 v4, v8, v4
+; GFX8-SDAG-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX8-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmax_v8f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x44
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, s8
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v1, 1.0, s16
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s9
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s17
+; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s10
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s18
+; GFX8-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s11
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v4, 1.0, s19
+; GFX8-GISEL-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v4, 1.0, s12
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v5, 1.0, s20
+; GFX8-GISEL-NEXT: v_max_f32_e32 v4, v4, v5
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v5, 1.0, s13
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v6, 1.0, s21
+; GFX8-GISEL-NEXT: v_max_f32_e32 v5, v5, v6
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v6, 1.0, s14
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v7, 1.0, s22
+; GFX8-GISEL-NEXT: v_max_f32_e32 v6, v6, v7
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v7, 1.0, s15
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v8, 1.0, s23
+; GFX8-GISEL-NEXT: v_max_f32_e32 v7, v7, v8
+; GFX8-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX8-GISEL-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmax_v8f32:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x44
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s19, s19
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s11, s11
+; GFX9-SDAG-NEXT: v_max_f32_e32 v3, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s18, s18
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s10, s10
+; GFX9-SDAG-NEXT: v_max_f32_e32 v2, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s17, s17
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s9, s9
+; GFX9-SDAG-NEXT: v_max_f32_e32 v1, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s16, s16
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s8, s8
+; GFX9-SDAG-NEXT: v_max_f32_e32 v0, v4, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s23, s23
+; GFX9-SDAG-NEXT: v_max_f32_e64 v5, s15, s15
+; GFX9-SDAG-NEXT: v_max_f32_e32 v7, v5, v4
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s22, s22
+; GFX9-SDAG-NEXT: v_max_f32_e64 v5, s14, s14
+; GFX9-SDAG-NEXT: v_max_f32_e32 v6, v5, v4
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s21, s21
+; GFX9-SDAG-NEXT: v_max_f32_e64 v5, s13, s13
+; GFX9-SDAG-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s20, s20
+; GFX9-SDAG-NEXT: v_max_f32_e64 v8, s12, s12
+; GFX9-SDAG-NEXT: v_max_f32_e32 v4, v8, v4
+; GFX9-SDAG-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX9-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmax_v8f32:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x44
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e64 v0, s8, s8
+; GFX9-GISEL-NEXT: v_max_f32_e64 v1, s16, s16
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s9, s9
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s17, s17
+; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s10, s10
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s18, s18
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s11, s11
+; GFX9-GISEL-NEXT: v_max_f32_e64 v4, s19, s19
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX9-GISEL-NEXT: v_max_f32_e64 v4, s12, s12
+; GFX9-GISEL-NEXT: v_max_f32_e64 v5, s20, s20
+; GFX9-GISEL-NEXT: v_max_f32_e32 v4, v4, v5
+; GFX9-GISEL-NEXT: v_max_f32_e64 v5, s13, s13
+; GFX9-GISEL-NEXT: v_max_f32_e64 v6, s21, s21
+; GFX9-GISEL-NEXT: v_max_f32_e32 v5, v5, v6
+; GFX9-GISEL-NEXT: v_max_f32_e64 v6, s14, s14
+; GFX9-GISEL-NEXT: v_max_f32_e64 v7, s22, s22
+; GFX9-GISEL-NEXT: v_max_f32_e32 v6, v6, v7
+; GFX9-GISEL-NEXT: v_max_f32_e64 v7, s15, s15
+; GFX9-GISEL-NEXT: v_max_f32_e64 v8, s23, s23
+; GFX9-GISEL-NEXT: v_max_f32_e32 v7, v7, v8
+; GFX9-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-GISEL-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmax_v8f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: s_load_b512 s[8:23], s[4:5], 0x44
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s19, s19
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s18, s18
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s17, s17
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s23, s23
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v10, s15, s15
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v11, s22, s22
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s14, s14
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s21, s21
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v14, s13, s13
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v15, s20, s20
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v16, s12, s12
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s16, s16
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s8, s8
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v1, v0 :: v_dual_max_num_f32 v2, v4, v2
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v6, v5 :: v_dual_max_num_f32 v6, v12, v11
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v7, v10, v7 :: v_dual_max_num_f32 v0, v9, v8
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v5, v14, v13 :: v_dual_max_num_f32 v4, v16, v15
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
+; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmax_v8f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0x44
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s8, s8
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s16, s16
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s9, s9
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s17, s17
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s10, s10
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v5, s18, s18
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v6, s11, s11
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v7, s19, s19
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v8, s12, s12
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v9, s20, s20
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v10, s13, s13
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v11, s21, s21
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v12, s14, s14
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v13, s22, s22
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v14, s15, s15
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v15, s23, s23
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v4
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s8, v5
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s9, v6
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s10, v7
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s11, v8
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s12, v9
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s13, v10
+; GFX12-GISEL-NEXT: s_max_num_f32 s4, s2, s3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v11
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v12
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s14, v13
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s15, v14
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s16, v15
+; GFX12-GISEL-NEXT: s_max_num_f32 s5, s5, s6
+; GFX12-GISEL-NEXT: s_max_num_f32 s6, s7, s8
+; GFX12-GISEL-NEXT: s_max_num_f32 s7, s9, s10
+; GFX12-GISEL-NEXT: s_max_num_f32 s8, s11, s12
+; GFX12-GISEL-NEXT: s_max_num_f32 s9, s13, s2
+; GFX12-GISEL-NEXT: s_max_num_f32 s10, s3, s14
+; GFX12-GISEL-NEXT: s_max_num_f32 s11, s15, s16
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-GISEL-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
+; GFX12-GISEL-NEXT: s_endpgm
%val = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %a, <8 x float> %b)
store <8 x float> %val, ptr addrspace(1) %out, align 32
ret void
}
-; GCN-LABEL: {{^}}test_fmax_v16f32:
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
define amdgpu_kernel void @test_fmax_v16f32(ptr addrspace(1) %out, <16 x float> %a, <16 x float> %b) #0 {
+; GFX8-SDAG-LABEL: test_fmax_v16f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx16 s[36:51], s[4:5], 0xa4
+; GFX8-SDAG-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s39
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s11
+; GFX8-SDAG-NEXT: v_max_f32_e32 v3, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s38
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s10
+; GFX8-SDAG-NEXT: v_max_f32_e32 v2, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s37
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s9
+; GFX8-SDAG-NEXT: v_max_f32_e32 v1, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s36
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s8
+; GFX8-SDAG-NEXT: v_max_f32_e32 v0, v4, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s43
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v5, 1.0, s15
+; GFX8-SDAG-NEXT: v_max_f32_e32 v7, v5, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s42
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v5, 1.0, s14
+; GFX8-SDAG-NEXT: v_max_f32_e32 v6, v5, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s41
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v5, 1.0, s13
+; GFX8-SDAG-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s40
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v8, 1.0, s12
+; GFX8-SDAG-NEXT: v_max_f32_e32 v4, v8, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v8, 1.0, s47
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v9, 1.0, s19
+; GFX8-SDAG-NEXT: v_max_f32_e32 v11, v9, v8
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v8, 1.0, s46
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v9, 1.0, s18
+; GFX8-SDAG-NEXT: v_max_f32_e32 v10, v9, v8
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v8, 1.0, s45
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v9, 1.0, s17
+; GFX8-SDAG-NEXT: v_max_f32_e32 v9, v9, v8
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v8, 1.0, s44
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v12, 1.0, s16
+; GFX8-SDAG-NEXT: v_max_f32_e32 v8, v12, v8
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v12, 1.0, s51
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v13, 1.0, s23
+; GFX8-SDAG-NEXT: v_max_f32_e32 v15, v13, v12
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v12, 1.0, s50
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v13, 1.0, s22
+; GFX8-SDAG-NEXT: v_max_f32_e32 v14, v13, v12
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v12, 1.0, s49
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v13, 1.0, s21
+; GFX8-SDAG-NEXT: v_max_f32_e32 v13, v13, v12
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v12, 1.0, s48
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v16, 1.0, s20
+; GFX8-SDAG-NEXT: v_max_f32_e32 v12, v16, v12
+; GFX8-SDAG-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
+; GFX8-SDAG-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
+; GFX8-SDAG-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX8-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmax_v16f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
+; GFX8-GISEL-NEXT: s_load_dwordx16 s[36:51], s[4:5], 0xa4
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, s8
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v1, 1.0, s36
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s9
+; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v1, 1.0, s37
+; GFX8-GISEL-NEXT: v_max_f32_e32 v1, v2, v1
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s10
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s38
+; GFX8-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s11
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v4, 1.0, s39
+; GFX8-GISEL-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v4, 1.0, s12
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v5, 1.0, s40
+; GFX8-GISEL-NEXT: v_max_f32_e32 v4, v4, v5
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v5, 1.0, s13
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v6, 1.0, s41
+; GFX8-GISEL-NEXT: v_max_f32_e32 v5, v5, v6
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v6, 1.0, s14
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v7, 1.0, s42
+; GFX8-GISEL-NEXT: v_max_f32_e32 v6, v6, v7
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v7, 1.0, s15
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v8, 1.0, s43
+; GFX8-GISEL-NEXT: v_max_f32_e32 v7, v7, v8
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v8, 1.0, s16
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v9, 1.0, s44
+; GFX8-GISEL-NEXT: v_max_f32_e32 v8, v8, v9
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v9, 1.0, s17
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v10, 1.0, s45
+; GFX8-GISEL-NEXT: v_max_f32_e32 v9, v9, v10
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v10, 1.0, s18
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v11, 1.0, s46
+; GFX8-GISEL-NEXT: v_max_f32_e32 v10, v10, v11
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v11, 1.0, s19
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v12, 1.0, s47
+; GFX8-GISEL-NEXT: v_max_f32_e32 v11, v11, v12
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v12, 1.0, s20
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v13, 1.0, s48
+; GFX8-GISEL-NEXT: v_max_f32_e32 v12, v12, v13
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v13, 1.0, s21
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v14, 1.0, s49
+; GFX8-GISEL-NEXT: v_max_f32_e32 v13, v13, v14
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v14, 1.0, s22
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v15, 1.0, s50
+; GFX8-GISEL-NEXT: v_max_f32_e32 v14, v14, v15
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v15, 1.0, s23
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v16, 1.0, s51
+; GFX8-GISEL-NEXT: v_max_f32_e32 v15, v15, v16
+; GFX8-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX8-GISEL-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX8-GISEL-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
+; GFX8-GISEL-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmax_v16f32:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx16 s[36:51], s[4:5], 0xa4
+; GFX9-SDAG-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s39, s39
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s11, s11
+; GFX9-SDAG-NEXT: v_max_f32_e32 v3, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s38, s38
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s10, s10
+; GFX9-SDAG-NEXT: v_max_f32_e32 v2, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s37, s37
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s9, s9
+; GFX9-SDAG-NEXT: v_max_f32_e32 v1, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s36, s36
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s8, s8
+; GFX9-SDAG-NEXT: v_max_f32_e32 v0, v4, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s43, s43
+; GFX9-SDAG-NEXT: v_max_f32_e64 v5, s15, s15
+; GFX9-SDAG-NEXT: v_max_f32_e32 v7, v5, v4
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s42, s42
+; GFX9-SDAG-NEXT: v_max_f32_e64 v5, s14, s14
+; GFX9-SDAG-NEXT: v_max_f32_e32 v6, v5, v4
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s41, s41
+; GFX9-SDAG-NEXT: v_max_f32_e64 v5, s13, s13
+; GFX9-SDAG-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s40, s40
+; GFX9-SDAG-NEXT: v_max_f32_e64 v8, s12, s12
+; GFX9-SDAG-NEXT: v_max_f32_e32 v4, v8, v4
+; GFX9-SDAG-NEXT: v_max_f32_e64 v8, s47, s47
+; GFX9-SDAG-NEXT: v_max_f32_e64 v9, s19, s19
+; GFX9-SDAG-NEXT: v_max_f32_e32 v11, v9, v8
+; GFX9-SDAG-NEXT: v_max_f32_e64 v8, s46, s46
+; GFX9-SDAG-NEXT: v_max_f32_e64 v9, s18, s18
+; GFX9-SDAG-NEXT: v_max_f32_e32 v10, v9, v8
+; GFX9-SDAG-NEXT: v_max_f32_e64 v8, s45, s45
+; GFX9-SDAG-NEXT: v_max_f32_e64 v9, s17, s17
+; GFX9-SDAG-NEXT: v_max_f32_e32 v9, v9, v8
+; GFX9-SDAG-NEXT: v_max_f32_e64 v8, s44, s44
+; GFX9-SDAG-NEXT: v_max_f32_e64 v12, s16, s16
+; GFX9-SDAG-NEXT: v_max_f32_e32 v8, v12, v8
+; GFX9-SDAG-NEXT: v_max_f32_e64 v12, s51, s51
+; GFX9-SDAG-NEXT: v_max_f32_e64 v13, s23, s23
+; GFX9-SDAG-NEXT: v_max_f32_e32 v15, v13, v12
+; GFX9-SDAG-NEXT: v_max_f32_e64 v12, s50, s50
+; GFX9-SDAG-NEXT: v_max_f32_e64 v13, s22, s22
+; GFX9-SDAG-NEXT: v_max_f32_e32 v14, v13, v12
+; GFX9-SDAG-NEXT: v_max_f32_e64 v12, s49, s49
+; GFX9-SDAG-NEXT: v_max_f32_e64 v13, s21, s21
+; GFX9-SDAG-NEXT: v_max_f32_e32 v13, v13, v12
+; GFX9-SDAG-NEXT: v_max_f32_e64 v12, s48, s48
+; GFX9-SDAG-NEXT: v_max_f32_e64 v16, s20, s20
+; GFX9-SDAG-NEXT: v_max_f32_e32 v12, v16, v12
+; GFX9-SDAG-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
+; GFX9-SDAG-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
+; GFX9-SDAG-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX9-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmax_v16f32:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
+; GFX9-GISEL-NEXT: s_load_dwordx16 s[36:51], s[4:5], 0xa4
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e64 v0, s8, s8
+; GFX9-GISEL-NEXT: v_max_f32_e64 v1, s36, s36
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s9, s9
+; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max_f32_e64 v1, s37, s37
+; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v1
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s10, s10
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s38, s38
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s11, s11
+; GFX9-GISEL-NEXT: v_max_f32_e64 v4, s39, s39
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX9-GISEL-NEXT: v_max_f32_e64 v4, s12, s12
+; GFX9-GISEL-NEXT: v_max_f32_e64 v5, s40, s40
+; GFX9-GISEL-NEXT: v_max_f32_e32 v4, v4, v5
+; GFX9-GISEL-NEXT: v_max_f32_e64 v5, s13, s13
+; GFX9-GISEL-NEXT: v_max_f32_e64 v6, s41, s41
+; GFX9-GISEL-NEXT: v_max_f32_e32 v5, v5, v6
+; GFX9-GISEL-NEXT: v_max_f32_e64 v6, s14, s14
+; GFX9-GISEL-NEXT: v_max_f32_e64 v7, s42, s42
+; GFX9-GISEL-NEXT: v_max_f32_e32 v6, v6, v7
+; GFX9-GISEL-NEXT: v_max_f32_e64 v7, s15, s15
+; GFX9-GISEL-NEXT: v_max_f32_e64 v8, s43, s43
+; GFX9-GISEL-NEXT: v_max_f32_e32 v7, v7, v8
+; GFX9-GISEL-NEXT: v_max_f32_e64 v8, s16, s16
+; GFX9-GISEL-NEXT: v_max_f32_e64 v9, s44, s44
+; GFX9-GISEL-NEXT: v_max_f32_e32 v8, v8, v9
+; GFX9-GISEL-NEXT: v_max_f32_e64 v9, s17, s17
+; GFX9-GISEL-NEXT: v_max_f32_e64 v10, s45, s45
+; GFX9-GISEL-NEXT: v_max_f32_e32 v9, v9, v10
+; GFX9-GISEL-NEXT: v_max_f32_e64 v10, s18, s18
+; GFX9-GISEL-NEXT: v_max_f32_e64 v11, s46, s46
+; GFX9-GISEL-NEXT: v_max_f32_e32 v10, v10, v11
+; GFX9-GISEL-NEXT: v_max_f32_e64 v11, s19, s19
+; GFX9-GISEL-NEXT: v_max_f32_e64 v12, s47, s47
+; GFX9-GISEL-NEXT: v_max_f32_e32 v11, v11, v12
+; GFX9-GISEL-NEXT: v_max_f32_e64 v12, s20, s20
+; GFX9-GISEL-NEXT: v_max_f32_e64 v13, s48, s48
+; GFX9-GISEL-NEXT: v_max_f32_e32 v12, v12, v13
+; GFX9-GISEL-NEXT: v_max_f32_e64 v13, s21, s21
+; GFX9-GISEL-NEXT: v_max_f32_e64 v14, s49, s49
+; GFX9-GISEL-NEXT: v_max_f32_e32 v13, v13, v14
+; GFX9-GISEL-NEXT: v_max_f32_e64 v14, s22, s22
+; GFX9-GISEL-NEXT: v_max_f32_e64 v15, s50, s50
+; GFX9-GISEL-NEXT: v_max_f32_e32 v14, v14, v15
+; GFX9-GISEL-NEXT: v_max_f32_e64 v15, s23, s23
+; GFX9-GISEL-NEXT: v_max_f32_e64 v16, s51, s51
+; GFX9-GISEL-NEXT: v_max_f32_e32 v15, v15, v16
+; GFX9-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-GISEL-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX9-GISEL-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
+; GFX9-GISEL-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmax_v16f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_clause 0x2
+; GFX12-SDAG-NEXT: s_load_b512 s[36:51], s[4:5], 0xa4
+; GFX12-SDAG-NEXT: s_load_b512 s[8:23], s[4:5], 0x64
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s39, s39
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s38, s38
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s37, s37
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s43, s43
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s15, s15
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s42, s42
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v10, s14, s14
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v11, s41, s41
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s13, s13
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s47, s47
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v14, s19, s19
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v1, v0 :: v_dual_max_num_f32 v2, v4, v2
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v7, v8, v7
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s46, s46
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s18, s18
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v1, v6, v5
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v6, v10, v9
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s45, s45
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s17, s17
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v5, v12, v11
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v18, s40, s40
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v19, s12, s12
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v10, v4, v0
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v9, v9, v8
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s51, s51
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s23, s23
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s50, s50
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v20, s49, s49
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v21, s21, s21
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v22, s48, s48
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v23, s20, s20
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v11, v14, v13
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s22, s22
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s44, s44
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v24, s16, s16
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v16, s36, s36
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v17, s8, s8
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v15, v8, v4
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v14, v13, v12
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v13, v21, v20 :: v_dual_max_num_f32 v12, v23, v22
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v8, v24, v0
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v4, v19, v18
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v17, v16
+; GFX12-SDAG-NEXT: s_clause 0x3
+; GFX12-SDAG-NEXT: buffer_store_b128 v[12:15], off, s[0:3], null offset:48
+; GFX12-SDAG-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null offset:32
+; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
+; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmax_v16f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x2
+; GFX12-GISEL-NEXT: s_load_b512 s[36:51], s[4:5], 0x64
+; GFX12-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0xa4
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s36, s36
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s8, s8
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s37, s37
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s9, s9
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s38, s38
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v5, s10, s10
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v6, s39, s39
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v7, s11, s11
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v8, s40, s40
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v9, s12, s12
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v11, s13, s13
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v4
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v5
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s11, v6
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s12, v7
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s13, v8
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s24, v9
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s42, s42
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s14, s14
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s43, s43
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s15, s15
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s44, s44
+; GFX12-GISEL-NEXT: s_max_num_f32 s8, s2, s3
+; GFX12-GISEL-NEXT: s_max_num_f32 s9, s4, s5
+; GFX12-GISEL-NEXT: s_max_num_f32 s10, s6, s7
+; GFX12-GISEL-NEXT: s_max_num_f32 s11, s11, s12
+; GFX12-GISEL-NEXT: s_max_num_f32 s4, s13, s24
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s12, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s13, v4
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s16, s16
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s45, s45
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s17, s17
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s46, s46
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s18, s18
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s14, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s15, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s16, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s17, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s18, v4
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s47, s47
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s19, s19
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s48, s48
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s20, s20
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s49, s49
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v10, s41, s41
+; GFX12-GISEL-NEXT: s_max_num_f32 s6, s2, s3
+; GFX12-GISEL-NEXT: s_max_num_f32 s7, s7, s12
+; GFX12-GISEL-NEXT: s_max_num_f32 s12, s13, s14
+; GFX12-GISEL-NEXT: s_max_num_f32 s13, s15, s16
+; GFX12-GISEL-NEXT: s_max_num_f32 s14, s17, s18
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s16, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s17, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s18, v4
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s21, s21
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s50, s50
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s22, s22
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s51, s51
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s23, s23
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s25, v10
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s26, v11
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s19, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s20, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s21, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s22, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s23, v4
+; GFX12-GISEL-NEXT: s_max_num_f32 s5, s25, s26
+; GFX12-GISEL-NEXT: s_max_num_f32 s15, s2, s3
+; GFX12-GISEL-NEXT: s_max_num_f32 s16, s16, s17
+; GFX12-GISEL-NEXT: s_max_num_f32 s17, s18, s19
+; GFX12-GISEL-NEXT: s_max_num_f32 s18, s20, s21
+; GFX12-GISEL-NEXT: s_max_num_f32 s19, s22, s23
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v13, s17
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v14, s18 :: v_dual_mov_b32 v15, s19
+; GFX12-GISEL-NEXT: s_clause 0x3
+; GFX12-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-GISEL-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
+; GFX12-GISEL-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null offset:32
+; GFX12-GISEL-NEXT: buffer_store_b128 v[12:15], off, s[0:3], null offset:48
+; GFX12-GISEL-NEXT: s_endpgm
%val = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %a, <16 x float> %b)
store <16 x float> %val, ptr addrspace(1) %out, align 64
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmax_f32:
-; GCN-NOT: v_max_f32_e32
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmax_f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 2.0
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmax_f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, 2.0
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmax_f32:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 2.0
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmax_f32:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 2.0
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmax_f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 2.0
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmax_f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 2.0
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.maxnum.f32(float 1.0, float 2.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmax_f32_nan_nan:
-; GCN-NOT: v_max_f32_e32
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32_nan_nan(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmax_f32_nan_nan:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmax_f32_nan_nan:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmax_f32_nan_nan:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmax_f32_nan_nan:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmax_f32_nan_nan:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmax_f32_nan_nan:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmax_f32_val_nan:
-; GCN-NOT: v_max_f32_e32
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32_val_nan(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmax_f32_val_nan:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmax_f32_val_nan:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmax_f32_val_nan:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmax_f32_val_nan:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmax_f32_val_nan:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmax_f32_val_nan:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.maxnum.f32(float 1.0, float 0x7FF8000000000000)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmax_f32_nan_val:
-; GCN-NOT: v_max_f32_e32
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32_nan_val(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmax_f32_nan_val:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmax_f32_nan_val:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmax_f32_nan_val:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmax_f32_nan_val:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmax_f32_nan_val:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmax_f32_nan_val:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 1.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmax_f32_p0_p0:
-; GCN-NOT: v_max_f32_e32
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32_p0_p0(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmax_f32_p0_p0:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmax_f32_p0_p0:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmax_f32_p0_p0:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmax_f32_p0_p0:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmax_f32_p0_p0:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmax_f32_p0_p0:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.maxnum.f32(float 0.0, float 0.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmax_f32_p0_n0:
-; GCN-NOT: v_max_f32_e32
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32_p0_n0(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmax_f32_p0_n0:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmax_f32_p0_n0:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmax_f32_p0_n0:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmax_f32_p0_n0:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmax_f32_p0_n0:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmax_f32_p0_n0:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.maxnum.f32(float 0.0, float -0.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmax_f32_n0_p0:
-; GCN-NOT: v_max_f32_e32
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32_n0_p0(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmax_f32_n0_p0:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmax_f32_n0_p0:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmax_f32_n0_p0:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmax_f32_n0_p0:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmax_f32_n0_p0:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmax_f32_n0_p0:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.maxnum.f32(float -0.0, float 0.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmax_f32_n0_n0:
-; GCN-NOT: v_max_f32_e32
-; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32_n0_n0(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmax_f32_n0_n0:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmax_f32_n0_n0:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmax_f32_n0_n0:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmax_f32_n0_n0:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmax_f32_n0_n0:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmax_f32_n0_n0:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.maxnum.f32(float -0.0, float -0.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}fmax_var_immediate_f32_no_ieee:
-; GCN: v_max_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0
define amdgpu_ps float @fmax_var_immediate_f32_no_ieee(float inreg %a) #0 {
+; GFX8-LABEL: fmax_var_immediate_f32_no_ieee:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_max_f32_e64 v0, s0, 2.0
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fmax_var_immediate_f32_no_ieee:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_max_f32_e64 v0, s0, 2.0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fmax_var_immediate_f32_no_ieee:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_max_num_f32 s0, s0, 2.0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
%val = call float @llvm.maxnum.f32(float %a, float 2.0)
ret float %val
}
-; GCN-LABEL: {{^}}fmax_immediate_var_f32_no_ieee:
-; GCN: v_max_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0
define amdgpu_ps float @fmax_immediate_var_f32_no_ieee(float inreg %a) #0 {
+; GFX8-LABEL: fmax_immediate_var_f32_no_ieee:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_max_f32_e64 v0, s0, 2.0
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fmax_immediate_var_f32_no_ieee:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_max_f32_e64 v0, s0, 2.0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fmax_immediate_var_f32_no_ieee:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_max_num_f32 s0, s0, 2.0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
%val = call float @llvm.maxnum.f32(float 2.0, float %a)
ret float %val
}
-; GCN-LABEL: {{^}}fmax_var_literal_f32_no_ieee:
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
-; GCN: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
define amdgpu_ps float @fmax_var_literal_f32_no_ieee(float inreg %a) #0 {
+; GFX8-LABEL: fmax_var_literal_f32_no_ieee:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x42c60000
+; GFX8-NEXT: v_max_f32_e32 v0, s0, v0
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fmax_var_literal_f32_no_ieee:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c60000
+; GFX9-NEXT: v_max_f32_e32 v0, s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fmax_var_literal_f32_no_ieee:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_max_num_f32 s0, s0, 0x42c60000
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
%val = call float @llvm.maxnum.f32(float %a, float 99.0)
ret float %val
}
-; GCN-LABEL: {{^}}fmax_literal_var_f32_no_ieee:
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
-; GCN: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
define amdgpu_ps float @fmax_literal_var_f32_no_ieee(float inreg %a) #0 {
+; GFX8-LABEL: fmax_literal_var_f32_no_ieee:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x42c60000
+; GFX8-NEXT: v_max_f32_e32 v0, s0, v0
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fmax_literal_var_f32_no_ieee:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c60000
+; GFX9-NEXT: v_max_f32_e32 v0, s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fmax_literal_var_f32_no_ieee:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_max_num_f32 s0, s0, 0x42c60000
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
%val = call float @llvm.maxnum.f32(float 99.0, float %a)
ret float %val
}
-; GCN-LABEL: {{^}}test_func_fmax_v3f32:
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN: v_max_f32_e32
-; GCN-NOT: v_max_f32
define <3 x float> @test_func_fmax_v3f32(<3 x float> %a, <3 x float> %b) #0 {
+; GFX8-SDAG-LABEL: test_func_fmax_v3f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; GFX8-SDAG-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; GFX8-SDAG-NEXT: v_max_f32_e32 v0, v0, v3
+; GFX8-SDAG-NEXT: v_mul_f32_e32 v3, 1.0, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; GFX8-SDAG-NEXT: v_max_f32_e32 v1, v1, v3
+; GFX8-SDAG-NEXT: v_mul_f32_e32 v3, 1.0, v5
+; GFX8-SDAG-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX8-SDAG-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: test_func_fmax_v3f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v4
+; GFX8-GISEL-NEXT: v_max_f32_e32 v1, v1, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v5
+; GFX8-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-SDAG-LABEL: test_func_fmax_v3f32:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e32 v3, v3, v3
+; GFX9-SDAG-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX9-SDAG-NEXT: v_max_f32_e32 v0, v0, v3
+; GFX9-SDAG-NEXT: v_max_f32_e32 v3, v4, v4
+; GFX9-SDAG-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX9-SDAG-NEXT: v_max_f32_e32 v1, v1, v3
+; GFX9-SDAG-NEXT: v_max_f32_e32 v3, v5, v5
+; GFX9-SDAG-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX9-SDAG-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: test_func_fmax_v3f32:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v3, v3
+; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v3
+; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v4, v4
+; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v1, v3
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v5, v5
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-LABEL: test_func_fmax_v3f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v3 :: v_dual_max_num_f32 v1, v1, v4
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v2, v2, v5
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: test_func_fmax_v3f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v3, v3, v3
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v4, v4, v4
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v5, v5, v5
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v3 :: v_dual_max_num_f32 v1, v1, v4
+; GFX12-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v5
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
%val = call <3 x float> @llvm.maxnum.v3f32(<3 x float> %a, <3 x float> %b)
ret <3 x float> %val
}
+define amdgpu_kernel void @test_fmax_f16_v_ieee_on(ptr addrspace(1) %out, half %a, half %b) #0 {
+; GFX8-SDAG-LABEL: test_fmax_f16_v_ieee_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: s_lshr_b32 s4, s6, 16
+; GFX8-SDAG-NEXT: v_max_f16_e64 v0, s4, s4
+; GFX8-SDAG-NEXT: v_max_f16_e64 v1, s6, s6
+; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmax_f16_v_ieee_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dword s3, s[4:5], 0x2c
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: s_lshr_b32 s4, s3, 16
+; GFX8-GISEL-NEXT: v_max_f16_e64 v0, s3, s3
+; GFX8-GISEL-NEXT: v_max_f16_e64 v1, s4, s4
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmax_f16_v_ieee_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: s_lshr_b32 s4, s6, 16
+; GFX9-SDAG-NEXT: v_max_f16_e64 v0, s4, s4
+; GFX9-SDAG-NEXT: v_max_f16_e64 v1, s6, s6
+; GFX9-SDAG-NEXT: v_max_f16_e32 v0, v1, v0
+; GFX9-SDAG-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmax_f16_v_ieee_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dword s3, s[4:5], 0x2c
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: s_lshr_b32 s4, s3, 16
+; GFX9-GISEL-NEXT: v_max_f16_e64 v0, s3, s3
+; GFX9-GISEL-NEXT: v_max_f16_e64 v1, s4, s4
+; GFX9-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmax_f16_v_ieee_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v1, s2, s2
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0, s3, s3
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f16_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmax_f16_v_ieee_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: s_lshr_b32 s3, s2, 16
+; GFX12-GISEL-NEXT: v_max_num_f16_e64 v0, s2, s2
+; GFX12-GISEL-NEXT: v_max_num_f16_e64 v1, s3, s3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: s_max_num_f16 s2, s2, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
+ %val = call half @llvm.maxnum.f16(half %a, half %b)
+ store half %val, ptr addrspace(1) %out, align 2
+ ret void
+}
+
+define amdgpu_ps half @test_fmax_f16_v_ieee_off(half %a, half %b) #0 {
+; GFX8-LABEL: test_fmax_f16_v_ieee_off:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmax_f16_v_ieee_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmax_f16_v_ieee_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX12-NEXT: ; return to shader part epilog
+ %val = call half @llvm.maxnum.f16(half %a, half %b)
+ ret half %val
+}
+
+define amdgpu_kernel void @test_fmax_f16_s_ieee_on(ptr addrspace(1) %out, half inreg %a, half inreg %b) #0 {
+; GFX8-SDAG-LABEL: test_fmax_f16_s_ieee_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: s_lshr_b32 s4, s6, 16
+; GFX8-SDAG-NEXT: v_max_f16_e64 v0, s4, s4
+; GFX8-SDAG-NEXT: v_max_f16_e64 v1, s6, s6
+; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmax_f16_s_ieee_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_mov_b32 s6, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-GISEL-NEXT: buffer_load_ushort v0, off, s[4:7], 0 offset:46
+; GFX8-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_max_f16_e64 v0, s0, s0
+; GFX8-GISEL-NEXT: v_max_f16_e64 v1, s1, s1
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: buffer_store_short v0, off, s[4:7], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmax_f16_s_ieee_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: s_lshr_b32 s4, s6, 16
+; GFX9-SDAG-NEXT: v_max_f16_e64 v0, s4, s4
+; GFX9-SDAG-NEXT: v_max_f16_e64 v1, s6, s6
+; GFX9-SDAG-NEXT: v_max_f16_e32 v0, v1, v0
+; GFX9-SDAG-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmax_f16_s_ieee_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_mov_b32 s6, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-GISEL-NEXT: buffer_load_ushort v0, off, s[4:7], 0 offset:46
+; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f16_e64 v1, s2, s2
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX9-GISEL-NEXT: v_max_f16_e64 v0, s2, s2
+; GFX9-GISEL-NEXT: v_max_f16_e32 v0, v1, v0
+; GFX9-GISEL-NEXT: s_mov_b64 s[2:3], s[6:7]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmax_f16_s_ieee_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v1, s2, s2
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0, s3, s3
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f16_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmax_f16_s_ieee_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x2
+; GFX12-GISEL-NEXT: s_load_u16 s2, s[4:5], 0x2c
+; GFX12-GISEL-NEXT: s_load_u16 s3, s[4:5], 0x2e
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f16_e64 v0, s2, s2
+; GFX12-GISEL-NEXT: v_max_num_f16_e64 v1, s3, s3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: s_max_num_f16 s2, s2, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
+ %val = call half @llvm.maxnum.f16(half %a, half %b)
+ store half %val, ptr addrspace(1) %out, align 2
+ ret void
+}
+
+define amdgpu_ps half @test_fmax_f16_s_ieee_off(half inreg %a, half inreg %b) #0 {
+; GFX8-LABEL: test_fmax_f16_s_ieee_off:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_max_f16_e32 v0, s0, v0
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmax_f16_s_ieee_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_max_f16_e32 v0, s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmax_f16_s_ieee_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_max_num_f16 s0, s0, s1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
+ %val = call half @llvm.maxnum.f16(half %a, half %b)
+ ret half %val
+}
+
+define amdgpu_kernel void @test_fmax_f32_s_ieee_on(ptr addrspace(1) %out, float inreg %a, float inreg %b) #0 {
+; GFX8-SDAG-LABEL: test_fmax_f32_s_ieee_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: s_mov_b64 s[4:5], s[2:3]
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s5
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s4
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_max_f32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmax_f32_s_ieee_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, s2
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v1, 1.0, s3
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmax_f32_s_ieee_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s3, s3
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s2, s2
+; GFX9-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX9-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX9-SDAG-NEXT: v_max_f32_e32 v0, v1, v0
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmax_f32_s_ieee_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e64 v0, s2, s2
+; GFX9-GISEL-NEXT: v_max_f32_e64 v1, s3, s3
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmax_f32_s_ieee_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s2, s2
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmax_f32_s_ieee_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s2, s2
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s3, s3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: s_max_num_f32 s2, s2, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
+ %val = call float @llvm.maxnum.f32(float %a, float %b)
+ store float %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_ps float @test_fmax_f32_s_ieee_off(float inreg %a, float inreg %b) #0 {
+; GFX8-LABEL: test_fmax_f32_s_ieee_off:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_max_f32_e32 v0, s0, v0
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmax_f32_s_ieee_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_max_f32_e32 v0, s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmax_f32_s_ieee_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_max_num_f32 s0, s0, s1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
+ %val = call float @llvm.maxnum.f32(float %a, float %b)
+ ret float %val
+}
+
+define amdgpu_kernel void @test_fmax_v2f16_v_ieee_on(ptr addrspace(1) %out, <2 x half> %a, <2 x half> %b) #0 {
+; GFX8-SDAG-LABEL: test_fmax_v2f16_v_ieee_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX8-SDAG-NEXT: s_lshr_b32 s0, s3, 16
+; GFX8-SDAG-NEXT: v_max_f16_e64 v0, s0, s0
+; GFX8-SDAG-NEXT: s_lshr_b32 s0, s2, 16
+; GFX8-SDAG-NEXT: v_max_f16_e64 v1, s0, s0
+; GFX8-SDAG-NEXT: v_max_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-SDAG-NEXT: v_max_f16_e64 v1, s3, s3
+; GFX8-SDAG-NEXT: v_max_f16_e64 v2, s2, s2
+; GFX8-SDAG-NEXT: v_max_f16_e32 v1, v2, v1
+; GFX8-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmax_v2f16_v_ieee_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_max_f16_e64 v0, s2, s2
+; GFX8-GISEL-NEXT: v_max_f16_e64 v1, s3, s3
+; GFX8-GISEL-NEXT: s_lshr_b32 s4, s2, 16
+; GFX8-GISEL-NEXT: s_lshr_b32 s5, s3, 16
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e64 v1, s4, s4
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX8-GISEL-NEXT: v_max_f16_e64 v0, s5, s5
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v1, v0
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX8-GISEL-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX8-GISEL-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX8-GISEL-NEXT: s_lshl_b32 s3, s3, 16
+; GFX8-GISEL-NEXT: s_or_b32 s2, s2, s3
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmax_v2f16_v_ieee_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_pk_max_f16 v0, s3, s3
+; GFX9-SDAG-NEXT: v_pk_max_f16 v1, s2, s2
+; GFX9-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX9-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX9-SDAG-NEXT: v_pk_max_f16 v0, v1, v0
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmax_v2f16_v_ieee_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_pk_max_f16 v0, s2, s2
+; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s3, s3
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: v_pk_max_f16 v0, v0, v1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmax_v2f16_v_ieee_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s3, s3
+; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, s2, s2
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v1, v0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmax_v2f16_v_ieee_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, s2, s2
+; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, s3, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
+ %val = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
+ store <2 x half> %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_ps <2 x half> @test_fmax_v2f16_v_ieee_off(<2 x half> %a, <2 x half> %b) #0 {
+; GFX8-SDAG-LABEL: test_fmax_v2f16_v_ieee_off:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: v_max_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX8-GISEL-LABEL: test_fmax_v2f16_v_ieee_off:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: v_max_f16_e32 v2, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-GISEL-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmax_v2f16_v_ieee_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmax_v2f16_v_ieee_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-NEXT: ; return to shader part epilog
+ %val = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
+ ret <2 x half> %val
+}
+
+define amdgpu_kernel void @test_fmax_v2f16_s_ieee_on(ptr addrspace(1) %out, <2 x half> inreg %a, <2 x half> inreg %b) #0 {
+; GFX8-SDAG-LABEL: test_fmax_v2f16_s_ieee_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX8-SDAG-NEXT: s_lshr_b32 s0, s3, 16
+; GFX8-SDAG-NEXT: v_max_f16_e64 v0, s0, s0
+; GFX8-SDAG-NEXT: s_lshr_b32 s0, s2, 16
+; GFX8-SDAG-NEXT: v_max_f16_e64 v1, s0, s0
+; GFX8-SDAG-NEXT: v_max_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-SDAG-NEXT: v_max_f16_e64 v1, s3, s3
+; GFX8-SDAG-NEXT: v_max_f16_e64 v2, s2, s2
+; GFX8-SDAG-NEXT: v_max_f16_e32 v1, v2, v1
+; GFX8-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmax_v2f16_s_ieee_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_max_f16_e64 v0, s2, s2
+; GFX8-GISEL-NEXT: v_max_f16_e64 v1, s3, s3
+; GFX8-GISEL-NEXT: s_lshr_b32 s4, s2, 16
+; GFX8-GISEL-NEXT: s_lshr_b32 s5, s3, 16
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e64 v1, s4, s4
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX8-GISEL-NEXT: v_max_f16_e64 v0, s5, s5
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v1, v0
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX8-GISEL-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX8-GISEL-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX8-GISEL-NEXT: s_lshl_b32 s3, s3, 16
+; GFX8-GISEL-NEXT: s_or_b32 s2, s2, s3
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmax_v2f16_s_ieee_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_pk_max_f16 v0, s3, s3
+; GFX9-SDAG-NEXT: v_pk_max_f16 v1, s2, s2
+; GFX9-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX9-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX9-SDAG-NEXT: v_pk_max_f16 v0, v1, v0
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmax_v2f16_s_ieee_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_pk_max_f16 v0, s2, s2
+; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s3, s3
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: v_pk_max_f16 v0, v0, v1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmax_v2f16_s_ieee_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s3, s3
+; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, s2, s2
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v1, v0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmax_v2f16_s_ieee_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, s2, s2
+; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, s3, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
+ %val = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
+ store <2 x half> %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_ps <2 x half> @test_fmax_v2f16_s_ieee_off(<2 x half> inreg %a, <2 x half> inreg %b) #0 {
+; GFX8-SDAG-LABEL: test_fmax_v2f16_s_ieee_off:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_lshr_b32 s2, s1, 16
+; GFX8-SDAG-NEXT: s_lshr_b32 s3, s0, 16
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-SDAG-NEXT: v_max_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-SDAG-NEXT: v_max_f16_e32 v1, s0, v1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX8-GISEL-LABEL: test_fmax_v2f16_s_ieee_off:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-GISEL-NEXT: s_lshr_b32 s3, s1, 16
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, s0, v0
+; GFX8-GISEL-NEXT: s_lshr_b32 s2, s0, 16
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, s2, v0
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX8-GISEL-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX8-GISEL-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-GISEL-NEXT: s_lshl_b32 s1, s1, 16
+; GFX8-GISEL-NEXT: s_or_b32 s0, s0, s1
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-GISEL-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmax_v2f16_s_ieee_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_pk_max_f16 v0, s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmax_v2f16_s_ieee_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_pk_max_num_f16 v0, s0, s1
+; GFX12-NEXT: ; return to shader part epilog
+ %val = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
+ ret <2 x half> %val
+}
+
+define amdgpu_kernel void @test_fmax_f64_v_ieee_on(ptr addrspace(1) %out, double %a, double %b) #0 {
+; GFX8-SDAG-LABEL: test_fmax_f64_v_ieee_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_max_f64 v[0:1], s[6:7], s[6:7]
+; GFX8-SDAG-NEXT: v_max_f64 v[2:3], s[2:3], s[2:3]
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_max_f64 v[0:1], v[2:3], v[0:1]
+; GFX8-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmax_f64_v_ieee_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_max_f64 v[0:1], s[2:3], s[2:3]
+; GFX8-GISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX8-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmax_f64_v_ieee_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f64 v[0:1], s[6:7], s[6:7]
+; GFX9-SDAG-NEXT: v_max_f64 v[2:3], s[2:3], s[2:3]
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_max_f64 v[0:1], v[2:3], v[0:1]
+; GFX9-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmax_f64_v_ieee_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f64 v[0:1], s[2:3], s[2:3]
+; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[6:7], s[6:7]
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX9-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmax_f64_v_ieee_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[6:7], s[6:7]
+; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], s[2:3], s[2:3]
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmax_f64_v_ieee_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[2:3]
+; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[2:3], s[4:5], s[4:5]
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-GISEL-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
+ %val = call double @llvm.maxnum.f64(double %a, double %b)
+ store double %val, ptr addrspace(1) %out, align 8
+ ret void
+}
+
+define amdgpu_ps double @test_fmax_f64_v_ieee_off(double %a, double %b) #0 {
+; GFX8-LABEL: test_fmax_f64_v_ieee_off:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmax_f64_v_ieee_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmax_f64_v_ieee_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: ; return to shader part epilog
+ %val = call double @llvm.maxnum.f64(double %a, double %b)
+ ret double %val
+}
+
+define amdgpu_kernel void @test_fmax_f64_s_ieee_on(ptr addrspace(1) %out, double inreg %a, double inreg %b) #0 {
+; GFX8-SDAG-LABEL: test_fmax_f64_s_ieee_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_max_f64 v[2:3], s[2:3], s[2:3]
+; GFX8-SDAG-NEXT: v_max_f64 v[0:1], s[4:5], s[4:5]
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_max_f64 v[0:1], v[2:3], v[0:1]
+; GFX8-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmax_f64_s_ieee_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_max_f64 v[0:1], s[2:3], s[2:3]
+; GFX8-GISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX8-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmax_f64_s_ieee_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f64 v[2:3], s[2:3], s[2:3]
+; GFX9-SDAG-NEXT: v_max_f64 v[0:1], s[6:7], s[6:7]
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_max_f64 v[0:1], v[2:3], v[0:1]
+; GFX9-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmax_f64_s_ieee_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f64 v[0:1], s[2:3], s[2:3]
+; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[6:7], s[6:7]
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX9-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmax_f64_s_ieee_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[6:7], s[6:7]
+; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], s[2:3], s[2:3]
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmax_f64_s_ieee_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[2:3]
+; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[2:3], s[4:5], s[4:5]
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-GISEL-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
+ %val = call double @llvm.maxnum.f64(double %a, double %b)
+ store double %val, ptr addrspace(1) %out, align 8
+ ret void
+}
+
+define amdgpu_ps double @test_fmax_f64_s_ieee_off(double inreg %a, double inreg %b) #0 {
+; GFX8-LABEL: test_fmax_f64_s_ieee_off:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_max_f64 v[0:1], s[0:1], v[0:1]
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmax_f64_s_ieee_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_max_f64 v[0:1], s[0:1], v[0:1]
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmax_f64_s_ieee_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_max_num_f64_e64 v[0:1], s[0:1], s[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-NEXT: ; return to shader part epilog
+ %val = call double @llvm.maxnum.f64(double %a, double %b)
+ ret double %val
+}
+
declare float @llvm.maxnum.f32(float, float) #1
declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>) #1
declare <3 x float> @llvm.maxnum.v3f32(<3 x float>, <3 x float>) #1
declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1
declare <8 x float> @llvm.maxnum.v8f32(<8 x float>, <8 x float>) #1
declare <16 x float> @llvm.maxnum.v16f32(<16 x float>, <16 x float>) #1
-declare double @llvm.maxnum.f64(double, double)
+declare half @llvm.maxnum.f16(half, half) #1
+declare double @llvm.maxnum.f64(double, double) #1
+declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>) #1
attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/AMDGPU/fminnum.ll b/llvm/test/CodeGen/AMDGPU/fminnum.ll
index 22bd13f2379cf..3a8006ee6a719 100644
--- a/llvm/test/CodeGen/AMDGPU/fminnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminnum.ll
@@ -1,229 +1,2638 @@
-; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
-
-; GCN-LABEL: {{^}}test_fmin_f32_ieee_mode_on:
-; GCN: v_mul_f32_e64 [[QUIET0:v[0-9]+]], 1.0, s{{[0-9]+}}
-; GCN: v_mul_f32_e64 [[QUIET1:v[0-9]+]], 1.0, s{{[0-9]+}}
-; GCN: v_min_f32_e32 [[RESULT:v[0-9]+]], [[QUIET1]], [[QUIET0]]
-; GCN-NOT: [[RESULT]]
-; GCN: buffer_store_dword [[RESULT]]
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX8,GFX8-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX8,GFX8-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx908 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx908 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL %s
+
define amdgpu_kernel void @test_fmin_f32_ieee_mode_on(ptr addrspace(1) %out, float %a, float %b) #0 {
+; GFX8-SDAG-LABEL: test_fmin_f32_ieee_mode_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: s_mov_b64 s[4:5], s[2:3]
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s5
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s4
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_min_f32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmin_f32_ieee_mode_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, s2
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v1, 1.0, s3
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmin_f32_ieee_mode_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s3, s3
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s2, s2
+; GFX9-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX9-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX9-SDAG-NEXT: v_min_f32_e32 v0, v1, v0
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmin_f32_ieee_mode_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e64 v0, s2, s2
+; GFX9-GISEL-NEXT: v_max_f32_e64 v1, s3, s3
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmin_f32_ieee_mode_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s2, s2
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmin_f32_ieee_mode_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s2, s2
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s3, s3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: s_min_num_f32 s2, s2, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.minnum.f32(float %a, float %b)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}test_fmin_nnan_f32_ieee_mode_on:
-; GCN: s_waitcnt
-; GCN-NEXT: v_min_f32_e32 v0, v0, v1
-; GCN-NEXT: s_setpc_b64
define float @test_fmin_nnan_f32_ieee_mode_on(float %a, float %b) #0 {
+; GFX8-LABEL: test_fmin_nnan_f32_ieee_mode_on:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: test_fmin_nnan_f32_ieee_mode_on:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmin_nnan_f32_ieee_mode_on:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%val = call nnan float @llvm.minnum.f32(float %a, float %b)
ret float %val
}
-; GCN-LABEL: {{^}}test_fmin_nnan_f32_ieee_mode_off:
-; GCN-NOT: v0
-; GCN-NOT: v1
-; GCN: v_min_f32_e32 v0, v0, v1
-; GCN-NEXT: ; return
define amdgpu_ps float @test_fmin_nnan_f32_ieee_mode_off(float %a, float %b) #0 {
+; GFX8-LABEL: test_fmin_nnan_f32_ieee_mode_off:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmin_nnan_f32_ieee_mode_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmin_nnan_f32_ieee_mode_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: ; return to shader part epilog
%val = call nnan float @llvm.minnum.f32(float %a, float %b)
ret float %val
}
-; GCN-LABEL: {{^}}test_fmin_f32_ieee_mode_off:
-; GCN: v_min_f32_e32 v0, v0, v1
-; GCN-NEXT: ; return
define amdgpu_ps float @test_fmin_f32_ieee_mode_off(float %a, float %b) #0 {
+; GFX8-LABEL: test_fmin_f32_ieee_mode_off:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmin_f32_ieee_mode_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmin_f32_ieee_mode_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: ; return to shader part epilog
%val = call float @llvm.minnum.f32(float %a, float %b)
ret float %val
}
-; GCN-LABEL: {{^}}test_fmin_v2f32:
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
define amdgpu_kernel void @test_fmin_v2f32(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b) #0 {
+; GFX8-SDAG-LABEL: test_fmin_v2f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s3
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s1
+; GFX8-SDAG-NEXT: v_min_f32_e32 v1, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s2
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v2, 1.0, s0
+; GFX8-SDAG-NEXT: v_min_f32_e32 v0, v2, v0
+; GFX8-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmin_v2f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_mov_b32 s6, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, s0
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v1, 1.0, s2
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s1
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s3
+; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
+; GFX8-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmin_v2f32:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s11, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s10, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s3, s3
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s1, s1
+; GFX9-SDAG-NEXT: v_min_f32_e32 v1, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s2, s2
+; GFX9-SDAG-NEXT: v_max_f32_e64 v2, s0, s0
+; GFX9-SDAG-NEXT: v_min_f32_e32 v0, v2, v0
+; GFX9-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmin_v2f32:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_mov_b32 s10, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s11, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e64 v0, s0, s0
+; GFX9-GISEL-NEXT: v_max_f32_e64 v1, s2, s2
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s1, s1
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s3, s3
+; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
+; GFX9-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmin_v2f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX12-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_mov_b32 s7, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s1, s1
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s2, s2
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v3, s0, s0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_dual_min_num_f32 v1, v1, v0 :: v_dual_min_num_f32 v0, v3, v2
+; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmin_v2f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_mov_b32 s6, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s7, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s0, s0
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s2, s2
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s1, s1
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s3, s3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX12-GISEL-NEXT: s_min_num_f32 s0, s0, s1
+; GFX12-GISEL-NEXT: s_min_num_f32 s1, s2, s3
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %b)
store <2 x float> %val, ptr addrspace(1) %out, align 8
ret void
}
-; GCN-LABEL: {{^}}test_fmin_v4f32:
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
define amdgpu_kernel void @test_fmin_v4f32(ptr addrspace(1) %out, <4 x float> %a, <4 x float> %b) #0 {
+; GFX8-SDAG-LABEL: test_fmin_v4f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s15
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s11
+; GFX8-SDAG-NEXT: v_min_f32_e32 v3, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s14
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s10
+; GFX8-SDAG-NEXT: v_min_f32_e32 v2, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s13
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s9
+; GFX8-SDAG-NEXT: v_min_f32_e32 v1, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s12
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s8
+; GFX8-SDAG-NEXT: v_min_f32_e32 v0, v4, v0
+; GFX8-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmin_v4f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, s8
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v1, 1.0, s12
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s9
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s13
+; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s10
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s14
+; GFX8-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s11
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v4, 1.0, s15
+; GFX8-GISEL-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX8-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmin_v4f32:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s15, s15
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s11, s11
+; GFX9-SDAG-NEXT: v_min_f32_e32 v3, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s14, s14
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s10, s10
+; GFX9-SDAG-NEXT: v_min_f32_e32 v2, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s13, s13
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s9, s9
+; GFX9-SDAG-NEXT: v_min_f32_e32 v1, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s12, s12
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s8, s8
+; GFX9-SDAG-NEXT: v_min_f32_e32 v0, v4, v0
+; GFX9-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmin_v4f32:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e64 v0, s8, s8
+; GFX9-GISEL-NEXT: v_max_f32_e64 v1, s12, s12
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s9, s9
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s13, s13
+; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s10, s10
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s14, s14
+; GFX9-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s11, s11
+; GFX9-GISEL-NEXT: v_max_f32_e64 v4, s15, s15
+; GFX9-GISEL-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX9-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmin_v4f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s15, s15
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s14, s14
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s13, s13
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s12, s12
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s8, s8
+; GFX12-SDAG-NEXT: v_dual_min_num_f32 v3, v1, v0 :: v_dual_min_num_f32 v2, v4, v2
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_dual_min_num_f32 v1, v6, v5 :: v_dual_min_num_f32 v0, v8, v7
+; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmin_v4f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s8, s8
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s12, s12
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s9, s9
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s13, s13
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s10, s10
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v5, s14, s14
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v6, s11, s11
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v7, s15, s15
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v4
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s8, v5
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s9, v6
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s10, v7
+; GFX12-GISEL-NEXT: s_min_num_f32 s4, s2, s3
+; GFX12-GISEL-NEXT: s_min_num_f32 s5, s5, s6
+; GFX12-GISEL-NEXT: s_min_num_f32 s6, s7, s8
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_min_num_f32 s7, s9, s10
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b)
store <4 x float> %val, ptr addrspace(1) %out, align 16
ret void
}
-; GCN-LABEL: {{^}}test_fmin_v8f32:
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
define amdgpu_kernel void @test_fmin_v8f32(ptr addrspace(1) %out, <8 x float> %a, <8 x float> %b) #0 {
+; GFX8-SDAG-LABEL: test_fmin_v8f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x44
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s19
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s11
+; GFX8-SDAG-NEXT: v_min_f32_e32 v3, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s18
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s10
+; GFX8-SDAG-NEXT: v_min_f32_e32 v2, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s17
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s9
+; GFX8-SDAG-NEXT: v_min_f32_e32 v1, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s16
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s8
+; GFX8-SDAG-NEXT: v_min_f32_e32 v0, v4, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s23
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v5, 1.0, s15
+; GFX8-SDAG-NEXT: v_min_f32_e32 v7, v5, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s22
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v5, 1.0, s14
+; GFX8-SDAG-NEXT: v_min_f32_e32 v6, v5, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s21
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v5, 1.0, s13
+; GFX8-SDAG-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s20
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v8, 1.0, s12
+; GFX8-SDAG-NEXT: v_min_f32_e32 v4, v8, v4
+; GFX8-SDAG-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX8-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmin_v8f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x44
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, s8
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v1, 1.0, s16
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s9
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s17
+; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s10
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s18
+; GFX8-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s11
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v4, 1.0, s19
+; GFX8-GISEL-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v4, 1.0, s12
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v5, 1.0, s20
+; GFX8-GISEL-NEXT: v_min_f32_e32 v4, v4, v5
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v5, 1.0, s13
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v6, 1.0, s21
+; GFX8-GISEL-NEXT: v_min_f32_e32 v5, v5, v6
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v6, 1.0, s14
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v7, 1.0, s22
+; GFX8-GISEL-NEXT: v_min_f32_e32 v6, v6, v7
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v7, 1.0, s15
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v8, 1.0, s23
+; GFX8-GISEL-NEXT: v_min_f32_e32 v7, v7, v8
+; GFX8-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX8-GISEL-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmin_v8f32:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x44
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s19, s19
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s11, s11
+; GFX9-SDAG-NEXT: v_min_f32_e32 v3, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s18, s18
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s10, s10
+; GFX9-SDAG-NEXT: v_min_f32_e32 v2, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s17, s17
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s9, s9
+; GFX9-SDAG-NEXT: v_min_f32_e32 v1, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s16, s16
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s8, s8
+; GFX9-SDAG-NEXT: v_min_f32_e32 v0, v4, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s23, s23
+; GFX9-SDAG-NEXT: v_max_f32_e64 v5, s15, s15
+; GFX9-SDAG-NEXT: v_min_f32_e32 v7, v5, v4
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s22, s22
+; GFX9-SDAG-NEXT: v_max_f32_e64 v5, s14, s14
+; GFX9-SDAG-NEXT: v_min_f32_e32 v6, v5, v4
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s21, s21
+; GFX9-SDAG-NEXT: v_max_f32_e64 v5, s13, s13
+; GFX9-SDAG-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s20, s20
+; GFX9-SDAG-NEXT: v_max_f32_e64 v8, s12, s12
+; GFX9-SDAG-NEXT: v_min_f32_e32 v4, v8, v4
+; GFX9-SDAG-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX9-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmin_v8f32:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x44
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e64 v0, s8, s8
+; GFX9-GISEL-NEXT: v_max_f32_e64 v1, s16, s16
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s9, s9
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s17, s17
+; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s10, s10
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s18, s18
+; GFX9-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s11, s11
+; GFX9-GISEL-NEXT: v_max_f32_e64 v4, s19, s19
+; GFX9-GISEL-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX9-GISEL-NEXT: v_max_f32_e64 v4, s12, s12
+; GFX9-GISEL-NEXT: v_max_f32_e64 v5, s20, s20
+; GFX9-GISEL-NEXT: v_min_f32_e32 v4, v4, v5
+; GFX9-GISEL-NEXT: v_max_f32_e64 v5, s13, s13
+; GFX9-GISEL-NEXT: v_max_f32_e64 v6, s21, s21
+; GFX9-GISEL-NEXT: v_min_f32_e32 v5, v5, v6
+; GFX9-GISEL-NEXT: v_max_f32_e64 v6, s14, s14
+; GFX9-GISEL-NEXT: v_max_f32_e64 v7, s22, s22
+; GFX9-GISEL-NEXT: v_min_f32_e32 v6, v6, v7
+; GFX9-GISEL-NEXT: v_max_f32_e64 v7, s15, s15
+; GFX9-GISEL-NEXT: v_max_f32_e64 v8, s23, s23
+; GFX9-GISEL-NEXT: v_min_f32_e32 v7, v7, v8
+; GFX9-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-GISEL-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmin_v8f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: s_load_b512 s[8:23], s[4:5], 0x44
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s19, s19
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s18, s18
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s17, s17
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s23, s23
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v10, s15, s15
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v11, s22, s22
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s14, s14
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s21, s21
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v14, s13, s13
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v15, s20, s20
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v16, s12, s12
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s16, s16
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s8, s8
+; GFX12-SDAG-NEXT: v_dual_min_num_f32 v3, v1, v0 :: v_dual_min_num_f32 v2, v4, v2
+; GFX12-SDAG-NEXT: v_dual_min_num_f32 v1, v6, v5 :: v_dual_min_num_f32 v6, v12, v11
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-SDAG-NEXT: v_dual_min_num_f32 v7, v10, v7 :: v_dual_min_num_f32 v0, v9, v8
+; GFX12-SDAG-NEXT: v_dual_min_num_f32 v5, v14, v13 :: v_dual_min_num_f32 v4, v16, v15
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
+; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmin_v8f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0x44
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s8, s8
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s16, s16
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s9, s9
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s17, s17
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s10, s10
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v5, s18, s18
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v6, s11, s11
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v7, s19, s19
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v8, s12, s12
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v9, s20, s20
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v10, s13, s13
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v11, s21, s21
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v12, s14, s14
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v13, s22, s22
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v14, s15, s15
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v15, s23, s23
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v4
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s8, v5
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s9, v6
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s10, v7
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s11, v8
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s12, v9
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s13, v10
+; GFX12-GISEL-NEXT: s_min_num_f32 s4, s2, s3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v11
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v12
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s14, v13
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s15, v14
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s16, v15
+; GFX12-GISEL-NEXT: s_min_num_f32 s5, s5, s6
+; GFX12-GISEL-NEXT: s_min_num_f32 s6, s7, s8
+; GFX12-GISEL-NEXT: s_min_num_f32 s7, s9, s10
+; GFX12-GISEL-NEXT: s_min_num_f32 s8, s11, s12
+; GFX12-GISEL-NEXT: s_min_num_f32 s9, s13, s2
+; GFX12-GISEL-NEXT: s_min_num_f32 s10, s3, s14
+; GFX12-GISEL-NEXT: s_min_num_f32 s11, s15, s16
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-GISEL-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
+; GFX12-GISEL-NEXT: s_endpgm
%val = call <8 x float> @llvm.minnum.v8f32(<8 x float> %a, <8 x float> %b)
store <8 x float> %val, ptr addrspace(1) %out, align 32
ret void
}
-; GCN-LABEL: {{^}}test_fmin_v16f32:
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
define amdgpu_kernel void @test_fmin_v16f32(ptr addrspace(1) %out, <16 x float> %a, <16 x float> %b) #0 {
+; GFX8-SDAG-LABEL: test_fmin_v16f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx16 s[36:51], s[4:5], 0xa4
+; GFX8-SDAG-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s39
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s11
+; GFX8-SDAG-NEXT: v_min_f32_e32 v3, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s38
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s10
+; GFX8-SDAG-NEXT: v_min_f32_e32 v2, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s37
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s9
+; GFX8-SDAG-NEXT: v_min_f32_e32 v1, v1, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s36
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s8
+; GFX8-SDAG-NEXT: v_min_f32_e32 v0, v4, v0
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s43
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v5, 1.0, s15
+; GFX8-SDAG-NEXT: v_min_f32_e32 v7, v5, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s42
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v5, 1.0, s14
+; GFX8-SDAG-NEXT: v_min_f32_e32 v6, v5, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s41
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v5, 1.0, s13
+; GFX8-SDAG-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v4, 1.0, s40
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v8, 1.0, s12
+; GFX8-SDAG-NEXT: v_min_f32_e32 v4, v8, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v8, 1.0, s47
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v9, 1.0, s19
+; GFX8-SDAG-NEXT: v_min_f32_e32 v11, v9, v8
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v8, 1.0, s46
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v9, 1.0, s18
+; GFX8-SDAG-NEXT: v_min_f32_e32 v10, v9, v8
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v8, 1.0, s45
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v9, 1.0, s17
+; GFX8-SDAG-NEXT: v_min_f32_e32 v9, v9, v8
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v8, 1.0, s44
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v12, 1.0, s16
+; GFX8-SDAG-NEXT: v_min_f32_e32 v8, v12, v8
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v12, 1.0, s51
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v13, 1.0, s23
+; GFX8-SDAG-NEXT: v_min_f32_e32 v15, v13, v12
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v12, 1.0, s50
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v13, 1.0, s22
+; GFX8-SDAG-NEXT: v_min_f32_e32 v14, v13, v12
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v12, 1.0, s49
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v13, 1.0, s21
+; GFX8-SDAG-NEXT: v_min_f32_e32 v13, v13, v12
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v12, 1.0, s48
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v16, 1.0, s20
+; GFX8-SDAG-NEXT: v_min_f32_e32 v12, v16, v12
+; GFX8-SDAG-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
+; GFX8-SDAG-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
+; GFX8-SDAG-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX8-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmin_v16f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
+; GFX8-GISEL-NEXT: s_load_dwordx16 s[36:51], s[4:5], 0xa4
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, s8
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v1, 1.0, s36
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s9
+; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v1, 1.0, s37
+; GFX8-GISEL-NEXT: v_min_f32_e32 v1, v2, v1
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v2, 1.0, s10
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s38
+; GFX8-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v3, 1.0, s11
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v4, 1.0, s39
+; GFX8-GISEL-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v4, 1.0, s12
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v5, 1.0, s40
+; GFX8-GISEL-NEXT: v_min_f32_e32 v4, v4, v5
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v5, 1.0, s13
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v6, 1.0, s41
+; GFX8-GISEL-NEXT: v_min_f32_e32 v5, v5, v6
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v6, 1.0, s14
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v7, 1.0, s42
+; GFX8-GISEL-NEXT: v_min_f32_e32 v6, v6, v7
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v7, 1.0, s15
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v8, 1.0, s43
+; GFX8-GISEL-NEXT: v_min_f32_e32 v7, v7, v8
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v8, 1.0, s16
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v9, 1.0, s44
+; GFX8-GISEL-NEXT: v_min_f32_e32 v8, v8, v9
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v9, 1.0, s17
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v10, 1.0, s45
+; GFX8-GISEL-NEXT: v_min_f32_e32 v9, v9, v10
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v10, 1.0, s18
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v11, 1.0, s46
+; GFX8-GISEL-NEXT: v_min_f32_e32 v10, v10, v11
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v11, 1.0, s19
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v12, 1.0, s47
+; GFX8-GISEL-NEXT: v_min_f32_e32 v11, v11, v12
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v12, 1.0, s20
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v13, 1.0, s48
+; GFX8-GISEL-NEXT: v_min_f32_e32 v12, v12, v13
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v13, 1.0, s21
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v14, 1.0, s49
+; GFX8-GISEL-NEXT: v_min_f32_e32 v13, v13, v14
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v14, 1.0, s22
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v15, 1.0, s50
+; GFX8-GISEL-NEXT: v_min_f32_e32 v14, v14, v15
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v15, 1.0, s23
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v16, 1.0, s51
+; GFX8-GISEL-NEXT: v_min_f32_e32 v15, v15, v16
+; GFX8-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX8-GISEL-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX8-GISEL-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
+; GFX8-GISEL-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmin_v16f32:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx16 s[36:51], s[4:5], 0xa4
+; GFX9-SDAG-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s39, s39
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s11, s11
+; GFX9-SDAG-NEXT: v_min_f32_e32 v3, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s38, s38
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s10, s10
+; GFX9-SDAG-NEXT: v_min_f32_e32 v2, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s37, s37
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s9, s9
+; GFX9-SDAG-NEXT: v_min_f32_e32 v1, v1, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s36, s36
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s8, s8
+; GFX9-SDAG-NEXT: v_min_f32_e32 v0, v4, v0
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s43, s43
+; GFX9-SDAG-NEXT: v_max_f32_e64 v5, s15, s15
+; GFX9-SDAG-NEXT: v_min_f32_e32 v7, v5, v4
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s42, s42
+; GFX9-SDAG-NEXT: v_max_f32_e64 v5, s14, s14
+; GFX9-SDAG-NEXT: v_min_f32_e32 v6, v5, v4
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s41, s41
+; GFX9-SDAG-NEXT: v_max_f32_e64 v5, s13, s13
+; GFX9-SDAG-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX9-SDAG-NEXT: v_max_f32_e64 v4, s40, s40
+; GFX9-SDAG-NEXT: v_max_f32_e64 v8, s12, s12
+; GFX9-SDAG-NEXT: v_min_f32_e32 v4, v8, v4
+; GFX9-SDAG-NEXT: v_max_f32_e64 v8, s47, s47
+; GFX9-SDAG-NEXT: v_max_f32_e64 v9, s19, s19
+; GFX9-SDAG-NEXT: v_min_f32_e32 v11, v9, v8
+; GFX9-SDAG-NEXT: v_max_f32_e64 v8, s46, s46
+; GFX9-SDAG-NEXT: v_max_f32_e64 v9, s18, s18
+; GFX9-SDAG-NEXT: v_min_f32_e32 v10, v9, v8
+; GFX9-SDAG-NEXT: v_max_f32_e64 v8, s45, s45
+; GFX9-SDAG-NEXT: v_max_f32_e64 v9, s17, s17
+; GFX9-SDAG-NEXT: v_min_f32_e32 v9, v9, v8
+; GFX9-SDAG-NEXT: v_max_f32_e64 v8, s44, s44
+; GFX9-SDAG-NEXT: v_max_f32_e64 v12, s16, s16
+; GFX9-SDAG-NEXT: v_min_f32_e32 v8, v12, v8
+; GFX9-SDAG-NEXT: v_max_f32_e64 v12, s51, s51
+; GFX9-SDAG-NEXT: v_max_f32_e64 v13, s23, s23
+; GFX9-SDAG-NEXT: v_min_f32_e32 v15, v13, v12
+; GFX9-SDAG-NEXT: v_max_f32_e64 v12, s50, s50
+; GFX9-SDAG-NEXT: v_max_f32_e64 v13, s22, s22
+; GFX9-SDAG-NEXT: v_min_f32_e32 v14, v13, v12
+; GFX9-SDAG-NEXT: v_max_f32_e64 v12, s49, s49
+; GFX9-SDAG-NEXT: v_max_f32_e64 v13, s21, s21
+; GFX9-SDAG-NEXT: v_min_f32_e32 v13, v13, v12
+; GFX9-SDAG-NEXT: v_max_f32_e64 v12, s48, s48
+; GFX9-SDAG-NEXT: v_max_f32_e64 v16, s20, s20
+; GFX9-SDAG-NEXT: v_min_f32_e32 v12, v16, v12
+; GFX9-SDAG-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
+; GFX9-SDAG-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
+; GFX9-SDAG-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX9-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmin_v16f32:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
+; GFX9-GISEL-NEXT: s_load_dwordx16 s[36:51], s[4:5], 0xa4
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e64 v0, s8, s8
+; GFX9-GISEL-NEXT: v_max_f32_e64 v1, s36, s36
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s9, s9
+; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max_f32_e64 v1, s37, s37
+; GFX9-GISEL-NEXT: v_min_f32_e32 v1, v2, v1
+; GFX9-GISEL-NEXT: v_max_f32_e64 v2, s10, s10
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s38, s38
+; GFX9-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e64 v3, s11, s11
+; GFX9-GISEL-NEXT: v_max_f32_e64 v4, s39, s39
+; GFX9-GISEL-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX9-GISEL-NEXT: v_max_f32_e64 v4, s12, s12
+; GFX9-GISEL-NEXT: v_max_f32_e64 v5, s40, s40
+; GFX9-GISEL-NEXT: v_min_f32_e32 v4, v4, v5
+; GFX9-GISEL-NEXT: v_max_f32_e64 v5, s13, s13
+; GFX9-GISEL-NEXT: v_max_f32_e64 v6, s41, s41
+; GFX9-GISEL-NEXT: v_min_f32_e32 v5, v5, v6
+; GFX9-GISEL-NEXT: v_max_f32_e64 v6, s14, s14
+; GFX9-GISEL-NEXT: v_max_f32_e64 v7, s42, s42
+; GFX9-GISEL-NEXT: v_min_f32_e32 v6, v6, v7
+; GFX9-GISEL-NEXT: v_max_f32_e64 v7, s15, s15
+; GFX9-GISEL-NEXT: v_max_f32_e64 v8, s43, s43
+; GFX9-GISEL-NEXT: v_min_f32_e32 v7, v7, v8
+; GFX9-GISEL-NEXT: v_max_f32_e64 v8, s16, s16
+; GFX9-GISEL-NEXT: v_max_f32_e64 v9, s44, s44
+; GFX9-GISEL-NEXT: v_min_f32_e32 v8, v8, v9
+; GFX9-GISEL-NEXT: v_max_f32_e64 v9, s17, s17
+; GFX9-GISEL-NEXT: v_max_f32_e64 v10, s45, s45
+; GFX9-GISEL-NEXT: v_min_f32_e32 v9, v9, v10
+; GFX9-GISEL-NEXT: v_max_f32_e64 v10, s18, s18
+; GFX9-GISEL-NEXT: v_max_f32_e64 v11, s46, s46
+; GFX9-GISEL-NEXT: v_min_f32_e32 v10, v10, v11
+; GFX9-GISEL-NEXT: v_max_f32_e64 v11, s19, s19
+; GFX9-GISEL-NEXT: v_max_f32_e64 v12, s47, s47
+; GFX9-GISEL-NEXT: v_min_f32_e32 v11, v11, v12
+; GFX9-GISEL-NEXT: v_max_f32_e64 v12, s20, s20
+; GFX9-GISEL-NEXT: v_max_f32_e64 v13, s48, s48
+; GFX9-GISEL-NEXT: v_min_f32_e32 v12, v12, v13
+; GFX9-GISEL-NEXT: v_max_f32_e64 v13, s21, s21
+; GFX9-GISEL-NEXT: v_max_f32_e64 v14, s49, s49
+; GFX9-GISEL-NEXT: v_min_f32_e32 v13, v13, v14
+; GFX9-GISEL-NEXT: v_max_f32_e64 v14, s22, s22
+; GFX9-GISEL-NEXT: v_max_f32_e64 v15, s50, s50
+; GFX9-GISEL-NEXT: v_min_f32_e32 v14, v14, v15
+; GFX9-GISEL-NEXT: v_max_f32_e64 v15, s23, s23
+; GFX9-GISEL-NEXT: v_max_f32_e64 v16, s51, s51
+; GFX9-GISEL-NEXT: v_min_f32_e32 v15, v15, v16
+; GFX9-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-GISEL-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX9-GISEL-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
+; GFX9-GISEL-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmin_v16f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_clause 0x2
+; GFX12-SDAG-NEXT: s_load_b512 s[36:51], s[4:5], 0xa4
+; GFX12-SDAG-NEXT: s_load_b512 s[8:23], s[4:5], 0x64
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s39, s39
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s38, s38
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s37, s37
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s43, s43
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s15, s15
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s42, s42
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v10, s14, s14
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v11, s41, s41
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s13, s13
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s47, s47
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v14, s19, s19
+; GFX12-SDAG-NEXT: v_dual_min_num_f32 v3, v1, v0 :: v_dual_min_num_f32 v2, v4, v2
+; GFX12-SDAG-NEXT: v_min_num_f32_e32 v7, v8, v7
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s46, s46
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s18, s18
+; GFX12-SDAG-NEXT: v_min_num_f32_e32 v1, v6, v5
+; GFX12-SDAG-NEXT: v_min_num_f32_e32 v6, v10, v9
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s45, s45
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s17, s17
+; GFX12-SDAG-NEXT: v_min_num_f32_e32 v5, v12, v11
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v18, s40, s40
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v19, s12, s12
+; GFX12-SDAG-NEXT: v_min_num_f32_e32 v10, v4, v0
+; GFX12-SDAG-NEXT: v_min_num_f32_e32 v9, v9, v8
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s51, s51
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s23, s23
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s50, s50
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v20, s49, s49
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v21, s21, s21
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v22, s48, s48
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v23, s20, s20
+; GFX12-SDAG-NEXT: v_min_num_f32_e32 v11, v14, v13
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s22, s22
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s44, s44
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v24, s16, s16
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v16, s36, s36
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v17, s8, s8
+; GFX12-SDAG-NEXT: v_min_num_f32_e32 v15, v8, v4
+; GFX12-SDAG-NEXT: v_min_num_f32_e32 v14, v13, v12
+; GFX12-SDAG-NEXT: v_dual_min_num_f32 v13, v21, v20 :: v_dual_min_num_f32 v12, v23, v22
+; GFX12-SDAG-NEXT: v_min_num_f32_e32 v8, v24, v0
+; GFX12-SDAG-NEXT: v_min_num_f32_e32 v4, v19, v18
+; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v17, v16
+; GFX12-SDAG-NEXT: s_clause 0x3
+; GFX12-SDAG-NEXT: buffer_store_b128 v[12:15], off, s[0:3], null offset:48
+; GFX12-SDAG-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null offset:32
+; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
+; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmin_v16f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x2
+; GFX12-GISEL-NEXT: s_load_b512 s[36:51], s[4:5], 0x64
+; GFX12-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0xa4
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s36, s36
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s8, s8
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s37, s37
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s9, s9
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s38, s38
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v5, s10, s10
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v6, s39, s39
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v7, s11, s11
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v8, s40, s40
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v9, s12, s12
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v11, s13, s13
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v4
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v5
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s11, v6
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s12, v7
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s13, v8
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s24, v9
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s42, s42
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s14, s14
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s43, s43
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s15, s15
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s44, s44
+; GFX12-GISEL-NEXT: s_min_num_f32 s8, s2, s3
+; GFX12-GISEL-NEXT: s_min_num_f32 s9, s4, s5
+; GFX12-GISEL-NEXT: s_min_num_f32 s10, s6, s7
+; GFX12-GISEL-NEXT: s_min_num_f32 s11, s11, s12
+; GFX12-GISEL-NEXT: s_min_num_f32 s4, s13, s24
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s12, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s13, v4
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s16, s16
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s45, s45
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s17, s17
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s46, s46
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s18, s18
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s14, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s15, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s16, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s17, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s18, v4
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s47, s47
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s19, s19
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s48, s48
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s20, s20
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s49, s49
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v10, s41, s41
+; GFX12-GISEL-NEXT: s_min_num_f32 s6, s2, s3
+; GFX12-GISEL-NEXT: s_min_num_f32 s7, s7, s12
+; GFX12-GISEL-NEXT: s_min_num_f32 s12, s13, s14
+; GFX12-GISEL-NEXT: s_min_num_f32 s13, s15, s16
+; GFX12-GISEL-NEXT: s_min_num_f32 s14, s17, s18
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s16, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s17, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s18, v4
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s21, s21
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s50, s50
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s22, s22
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s51, s51
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s23, s23
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s25, v10
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s26, v11
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s19, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s20, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s21, v2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s22, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s23, v4
+; GFX12-GISEL-NEXT: s_min_num_f32 s5, s25, s26
+; GFX12-GISEL-NEXT: s_min_num_f32 s15, s2, s3
+; GFX12-GISEL-NEXT: s_min_num_f32 s16, s16, s17
+; GFX12-GISEL-NEXT: s_min_num_f32 s17, s18, s19
+; GFX12-GISEL-NEXT: s_min_num_f32 s18, s20, s21
+; GFX12-GISEL-NEXT: s_min_num_f32 s19, s22, s23
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v13, s17
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v14, s18 :: v_dual_mov_b32 v15, s19
+; GFX12-GISEL-NEXT: s_clause 0x3
+; GFX12-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-GISEL-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
+; GFX12-GISEL-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null offset:32
+; GFX12-GISEL-NEXT: buffer_store_b128 v[12:15], off, s[0:3], null offset:48
+; GFX12-GISEL-NEXT: s_endpgm
%val = call <16 x float> @llvm.minnum.v16f32(<16 x float> %a, <16 x float> %b)
store <16 x float> %val, ptr addrspace(1) %out, align 64
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmin_f32:
-; GCN-NOT: v_min_f32_e32
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmin_f32(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmin_f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmin_f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmin_f32:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmin_f32:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmin_f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmin_f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.minnum.f32(float 1.0, float 2.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmin_f32_nan_nan:
-; GCN-NOT: v_min_f32_e32
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmin_f32_nan_nan(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmin_f32_nan_nan:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmin_f32_nan_nan:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmin_f32_nan_nan:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmin_f32_nan_nan:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmin_f32_nan_nan:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmin_f32_nan_nan:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmin_f32_val_nan:
-; GCN-NOT: v_min_f32_e32
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmin_f32_val_nan(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmin_f32_val_nan:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmin_f32_val_nan:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmin_f32_val_nan:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmin_f32_val_nan:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmin_f32_val_nan:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmin_f32_val_nan:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.minnum.f32(float 1.0, float 0x7FF8000000000000)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmin_f32_nan_val:
-; GCN-NOT: v_min_f32_e32
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmin_f32_nan_val(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmin_f32_nan_val:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmin_f32_nan_val:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmin_f32_nan_val:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmin_f32_nan_val:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmin_f32_nan_val:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmin_f32_nan_val:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 1.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmin_f32_p0_p0:
-; GCN-NOT: v_min_f32_e32
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmin_f32_p0_p0(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmin_f32_p0_p0:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmin_f32_p0_p0:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmin_f32_p0_p0:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmin_f32_p0_p0:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmin_f32_p0_p0:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmin_f32_p0_p0:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.minnum.f32(float 0.0, float 0.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmin_f32_p0_n0:
-; GCN-NOT: v_min_f32_e32
-; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmin_f32_p0_n0(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmin_f32_p0_n0:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmin_f32_p0_n0:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmin_f32_p0_n0:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmin_f32_p0_n0:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmin_f32_p0_n0:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmin_f32_p0_n0:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.minnum.f32(float 0.0, float -0.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmin_f32_n0_p0:
-; GCN-NOT: v_min_f32_e32
-; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmin_f32_n0_p0(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmin_f32_n0_p0:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmin_f32_n0_p0:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmin_f32_n0_p0:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmin_f32_n0_p0:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmin_f32_n0_p0:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmin_f32_n0_p0:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.minnum.f32(float -0.0, float 0.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}constant_fold_fmin_f32_n0_n0:
-; GCN-NOT: v_min_f32_e32
-; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
-; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmin_f32_n0_n0(ptr addrspace(1) %out) #0 {
+; GFX8-SDAG-LABEL: constant_fold_fmin_f32_n0_n0:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: constant_fold_fmin_f32_n0_n0:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: constant_fold_fmin_f32_n0_n0:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: constant_fold_fmin_f32_n0_n0:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: constant_fold_fmin_f32_n0_n0:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: constant_fold_fmin_f32_n0_n0:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: v_bfrev_b32_e32 v0, 1
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
%val = call float @llvm.minnum.f32(float -0.0, float -0.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}fmin_var_immediate_f32_no_ieee:
-; GCN: v_min_f32_e32 v0, 2.0, v0
define amdgpu_ps float @fmin_var_immediate_f32_no_ieee(float %a) #0 {
+; GFX8-LABEL: fmin_var_immediate_f32_no_ieee:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_min_f32_e32 v0, 2.0, v0
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fmin_var_immediate_f32_no_ieee:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_min_f32_e32 v0, 2.0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fmin_var_immediate_f32_no_ieee:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_min_num_f32_e32 v0, 2.0, v0
+; GFX12-NEXT: ; return to shader part epilog
%val = call float @llvm.minnum.f32(float %a, float 2.0)
ret float %val
}
-; GCN-LABEL: {{^}}fmin_immediate_var_f32_no_ieee:
-; GCN: v_min_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0
define amdgpu_ps float @fmin_immediate_var_f32_no_ieee(float inreg %a) #0 {
+; GFX8-LABEL: fmin_immediate_var_f32_no_ieee:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_min_f32_e64 v0, s0, 2.0
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fmin_immediate_var_f32_no_ieee:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_min_f32_e64 v0, s0, 2.0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fmin_immediate_var_f32_no_ieee:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_min_num_f32 s0, s0, 2.0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
%val = call float @llvm.minnum.f32(float 2.0, float %a)
ret float %val
}
-; GCN-LABEL: {{^}}fmin_var_literal_f32_no_ieee:
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
-; GCN: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
define amdgpu_ps float @fmin_var_literal_f32_no_ieee(float inreg %a) #0 {
+; GFX8-LABEL: fmin_var_literal_f32_no_ieee:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x42c60000
+; GFX8-NEXT: v_min_f32_e32 v0, s0, v0
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fmin_var_literal_f32_no_ieee:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c60000
+; GFX9-NEXT: v_min_f32_e32 v0, s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fmin_var_literal_f32_no_ieee:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_min_num_f32 s0, s0, 0x42c60000
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
%val = call float @llvm.minnum.f32(float %a, float 99.0)
ret float %val
}
-; GCN-LABEL: {{^}}fmin_literal_var_f32_no_ieee:
-; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
-; GCN: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
define amdgpu_ps float @fmin_literal_var_f32_no_ieee(float inreg %a) #0 {
+; GFX8-LABEL: fmin_literal_var_f32_no_ieee:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x42c60000
+; GFX8-NEXT: v_min_f32_e32 v0, s0, v0
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fmin_literal_var_f32_no_ieee:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c60000
+; GFX9-NEXT: v_min_f32_e32 v0, s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fmin_literal_var_f32_no_ieee:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_min_num_f32 s0, s0, 0x42c60000
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
%val = call float @llvm.minnum.f32(float 99.0, float %a)
ret float %val
}
-; GCN-LABEL: {{^}}test_func_fmin_v3f32:
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN: v_min_f32_e32
-; GCN-NOT: v_min_f32
define <3 x float> @test_func_fmin_v3f32(<3 x float> %a, <3 x float> %b) nounwind {
+; GFX8-SDAG-LABEL: test_func_fmin_v3f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; GFX8-SDAG-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; GFX8-SDAG-NEXT: v_min_f32_e32 v0, v0, v3
+; GFX8-SDAG-NEXT: v_mul_f32_e32 v3, 1.0, v4
+; GFX8-SDAG-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; GFX8-SDAG-NEXT: v_min_f32_e32 v1, v1, v3
+; GFX8-SDAG-NEXT: v_mul_f32_e32 v3, 1.0, v5
+; GFX8-SDAG-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX8-SDAG-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: test_func_fmin_v3f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v4
+; GFX8-GISEL-NEXT: v_min_f32_e32 v1, v1, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v5
+; GFX8-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-SDAG-LABEL: test_func_fmin_v3f32:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e32 v3, v3, v3
+; GFX9-SDAG-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX9-SDAG-NEXT: v_min_f32_e32 v0, v0, v3
+; GFX9-SDAG-NEXT: v_max_f32_e32 v3, v4, v4
+; GFX9-SDAG-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX9-SDAG-NEXT: v_min_f32_e32 v1, v1, v3
+; GFX9-SDAG-NEXT: v_max_f32_e32 v3, v5, v5
+; GFX9-SDAG-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX9-SDAG-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: test_func_fmin_v3f32:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v3, v3
+; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v3
+; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v4, v4
+; GFX9-GISEL-NEXT: v_min_f32_e32 v1, v1, v3
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v5, v5
+; GFX9-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-LABEL: test_func_fmin_v3f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-SDAG-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
+; GFX12-SDAG-NEXT: v_min_num_f32_e32 v2, v2, v5
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: test_func_fmin_v3f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v3, v3, v3
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v4, v4, v4
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v5, v5, v5
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
+; GFX12-GISEL-NEXT: v_min_num_f32_e32 v2, v2, v5
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
%val = call <3 x float> @llvm.minnum.v3f32(<3 x float> %a, <3 x float> %b)
ret <3 x float> %val
}
+define amdgpu_kernel void @test_fmin_f16_v_ieee_on(ptr addrspace(1) %out, half %a, half %b) #0 {
+; GFX8-SDAG-LABEL: test_fmin_f16_v_ieee_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: s_lshr_b32 s4, s6, 16
+; GFX8-SDAG-NEXT: v_max_f16_e64 v0, s4, s4
+; GFX8-SDAG-NEXT: v_max_f16_e64 v1, s6, s6
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmin_f16_v_ieee_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dword s3, s[4:5], 0x2c
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: s_lshr_b32 s4, s3, 16
+; GFX8-GISEL-NEXT: v_max_f16_e64 v0, s3, s3
+; GFX8-GISEL-NEXT: v_max_f16_e64 v1, s4, s4
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmin_f16_v_ieee_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: s_lshr_b32 s4, s6, 16
+; GFX9-SDAG-NEXT: v_max_f16_e64 v0, s4, s4
+; GFX9-SDAG-NEXT: v_max_f16_e64 v1, s6, s6
+; GFX9-SDAG-NEXT: v_min_f16_e32 v0, v1, v0
+; GFX9-SDAG-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmin_f16_v_ieee_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dword s3, s[4:5], 0x2c
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: s_lshr_b32 s4, s3, 16
+; GFX9-GISEL-NEXT: v_max_f16_e64 v0, s3, s3
+; GFX9-GISEL-NEXT: v_max_f16_e64 v1, s4, s4
+; GFX9-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmin_f16_v_ieee_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v1, s2, s2
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0, s3, s3
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f16_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmin_f16_v_ieee_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: s_lshr_b32 s3, s2, 16
+; GFX12-GISEL-NEXT: v_max_num_f16_e64 v0, s2, s2
+; GFX12-GISEL-NEXT: v_max_num_f16_e64 v1, s3, s3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: s_min_num_f16 s2, s2, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
+ %val = call half @llvm.minnum.f16(half %a, half %b)
+ store half %val, ptr addrspace(1) %out, align 2
+ ret void
+}
+
+define amdgpu_ps half @test_fmin_f16_v_ieee_off(half %a, half %b) #0 {
+; GFX8-LABEL: test_fmin_f16_v_ieee_off:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmin_f16_v_ieee_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmin_f16_v_ieee_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-NEXT: ; return to shader part epilog
+ %val = call half @llvm.minnum.f16(half %a, half %b)
+ ret half %val
+}
+
+define amdgpu_kernel void @test_fmin_f16_s_ieee_on(ptr addrspace(1) %out, half inreg %a, half inreg %b) #0 {
+; GFX8-SDAG-LABEL: test_fmin_f16_s_ieee_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: s_lshr_b32 s4, s6, 16
+; GFX8-SDAG-NEXT: v_max_f16_e64 v0, s4, s4
+; GFX8-SDAG-NEXT: v_max_f16_e64 v1, s6, s6
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmin_f16_s_ieee_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_mov_b32 s6, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-GISEL-NEXT: buffer_load_ushort v0, off, s[4:7], 0 offset:46
+; GFX8-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_max_f16_e64 v0, s0, s0
+; GFX8-GISEL-NEXT: v_max_f16_e64 v1, s1, s1
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: buffer_store_short v0, off, s[4:7], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmin_f16_s_ieee_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: s_lshr_b32 s4, s6, 16
+; GFX9-SDAG-NEXT: v_max_f16_e64 v0, s4, s4
+; GFX9-SDAG-NEXT: v_max_f16_e64 v1, s6, s6
+; GFX9-SDAG-NEXT: v_min_f16_e32 v0, v1, v0
+; GFX9-SDAG-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmin_f16_s_ieee_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_mov_b32 s6, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-GISEL-NEXT: buffer_load_ushort v0, off, s[4:7], 0 offset:46
+; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f16_e64 v1, s2, s2
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX9-GISEL-NEXT: v_max_f16_e64 v0, s2, s2
+; GFX9-GISEL-NEXT: v_min_f16_e32 v0, v1, v0
+; GFX9-GISEL-NEXT: s_mov_b64 s[2:3], s[6:7]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmin_f16_s_ieee_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v1, s2, s2
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0, s3, s3
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f16_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmin_f16_s_ieee_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x2
+; GFX12-GISEL-NEXT: s_load_u16 s2, s[4:5], 0x2c
+; GFX12-GISEL-NEXT: s_load_u16 s3, s[4:5], 0x2e
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f16_e64 v0, s2, s2
+; GFX12-GISEL-NEXT: v_max_num_f16_e64 v1, s3, s3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: s_min_num_f16 s2, s2, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
+ %val = call half @llvm.minnum.f16(half %a, half %b)
+ store half %val, ptr addrspace(1) %out, align 2
+ ret void
+}
+
+define amdgpu_ps half @test_fmin_f16_s_ieee_off(half inreg %a, half inreg %b) #0 {
+; GFX8-LABEL: test_fmin_f16_s_ieee_off:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_min_f16_e32 v0, s0, v0
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmin_f16_s_ieee_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_min_f16_e32 v0, s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmin_f16_s_ieee_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_min_num_f16 s0, s0, s1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
+ %val = call half @llvm.minnum.f16(half %a, half %b)
+ ret half %val
+}
+
+define amdgpu_kernel void @test_fmin_f32_s_ieee_on(ptr addrspace(1) %out, float inreg %a, float inreg %b) #0 {
+; GFX8-SDAG-LABEL: test_fmin_f32_s_ieee_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: s_mov_b64 s[4:5], s[2:3]
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v0, 1.0, s5
+; GFX8-SDAG-NEXT: v_mul_f32_e64 v1, 1.0, s4
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_min_f32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmin_f32_s_ieee_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, s2
+; GFX8-GISEL-NEXT: v_mul_f32_e64 v1, 1.0, s3
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmin_f32_s_ieee_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f32_e64 v0, s3, s3
+; GFX9-SDAG-NEXT: v_max_f32_e64 v1, s2, s2
+; GFX9-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX9-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX9-SDAG-NEXT: v_min_f32_e32 v0, v1, v0
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmin_f32_s_ieee_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e64 v0, s2, s2
+; GFX9-GISEL-NEXT: v_max_f32_e64 v1, s3, s3
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmin_f32_s_ieee_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
+; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s2, s2
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmin_f32_s_ieee_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s2, s2
+; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s3, s3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: s_min_num_f32 s2, s2, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
+ %val = call float @llvm.minnum.f32(float %a, float %b)
+ store float %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_ps float @test_fmin_f32_s_ieee_off(float inreg %a, float inreg %b) #0 {
+; GFX8-LABEL: test_fmin_f32_s_ieee_off:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_min_f32_e32 v0, s0, v0
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmin_f32_s_ieee_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_min_f32_e32 v0, s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmin_f32_s_ieee_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_min_num_f32 s0, s0, s1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
+ %val = call float @llvm.minnum.f32(float %a, float %b)
+ ret float %val
+}
+
+define amdgpu_kernel void @test_fmin_v2f16_v_ieee_on(ptr addrspace(1) %out, <2 x half> %a, <2 x half> %b) #0 {
+; GFX8-SDAG-LABEL: test_fmin_v2f16_v_ieee_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX8-SDAG-NEXT: s_lshr_b32 s0, s3, 16
+; GFX8-SDAG-NEXT: v_max_f16_e64 v0, s0, s0
+; GFX8-SDAG-NEXT: s_lshr_b32 s0, s2, 16
+; GFX8-SDAG-NEXT: v_max_f16_e64 v1, s0, s0
+; GFX8-SDAG-NEXT: v_min_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-SDAG-NEXT: v_max_f16_e64 v1, s3, s3
+; GFX8-SDAG-NEXT: v_max_f16_e64 v2, s2, s2
+; GFX8-SDAG-NEXT: v_min_f16_e32 v1, v2, v1
+; GFX8-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmin_v2f16_v_ieee_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_max_f16_e64 v0, s2, s2
+; GFX8-GISEL-NEXT: v_max_f16_e64 v1, s3, s3
+; GFX8-GISEL-NEXT: s_lshr_b32 s4, s2, 16
+; GFX8-GISEL-NEXT: s_lshr_b32 s5, s3, 16
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e64 v1, s4, s4
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX8-GISEL-NEXT: v_max_f16_e64 v0, s5, s5
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v1, v0
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX8-GISEL-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX8-GISEL-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX8-GISEL-NEXT: s_lshl_b32 s3, s3, 16
+; GFX8-GISEL-NEXT: s_or_b32 s2, s2, s3
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmin_v2f16_v_ieee_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_pk_max_f16 v0, s3, s3
+; GFX9-SDAG-NEXT: v_pk_max_f16 v1, s2, s2
+; GFX9-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX9-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX9-SDAG-NEXT: v_pk_min_f16 v0, v1, v0
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmin_v2f16_v_ieee_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_pk_max_f16 v0, s2, s2
+; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s3, s3
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: v_pk_min_f16 v0, v0, v1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmin_v2f16_v_ieee_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s3, s3
+; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, s2, s2
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, v1, v0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmin_v2f16_v_ieee_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, s2, s2
+; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, s3, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
+ %val = call <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b)
+ store <2 x half> %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_ps <2 x half> @test_fmin_v2f16_v_ieee_off(<2 x half> %a, <2 x half> %b) #0 {
+; GFX8-SDAG-LABEL: test_fmin_v2f16_v_ieee_off:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: v_min_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX8-GISEL-LABEL: test_fmin_v2f16_v_ieee_off:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: v_min_f16_e32 v2, v0, v1
+; GFX8-GISEL-NEXT: v_min_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-GISEL-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmin_v2f16_v_ieee_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_pk_min_f16 v0, v0, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmin_v2f16_v_ieee_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-NEXT: ; return to shader part epilog
+ %val = call <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b)
+ ret <2 x half> %val
+}
+
+define amdgpu_kernel void @test_fmin_v2f16_s_ieee_on(ptr addrspace(1) %out, <2 x half> inreg %a, <2 x half> inreg %b) #0 {
+; GFX8-SDAG-LABEL: test_fmin_v2f16_s_ieee_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX8-SDAG-NEXT: s_lshr_b32 s0, s3, 16
+; GFX8-SDAG-NEXT: v_max_f16_e64 v0, s0, s0
+; GFX8-SDAG-NEXT: s_lshr_b32 s0, s2, 16
+; GFX8-SDAG-NEXT: v_max_f16_e64 v1, s0, s0
+; GFX8-SDAG-NEXT: v_min_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-SDAG-NEXT: v_max_f16_e64 v1, s3, s3
+; GFX8-SDAG-NEXT: v_max_f16_e64 v2, s2, s2
+; GFX8-SDAG-NEXT: v_min_f16_e32 v1, v2, v1
+; GFX8-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmin_v2f16_s_ieee_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_max_f16_e64 v0, s2, s2
+; GFX8-GISEL-NEXT: v_max_f16_e64 v1, s3, s3
+; GFX8-GISEL-NEXT: s_lshr_b32 s4, s2, 16
+; GFX8-GISEL-NEXT: s_lshr_b32 s5, s3, 16
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e64 v1, s4, s4
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX8-GISEL-NEXT: v_max_f16_e64 v0, s5, s5
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v1, v0
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX8-GISEL-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX8-GISEL-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX8-GISEL-NEXT: s_lshl_b32 s3, s3, 16
+; GFX8-GISEL-NEXT: s_or_b32 s2, s2, s3
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmin_v2f16_s_ieee_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_pk_max_f16 v0, s3, s3
+; GFX9-SDAG-NEXT: v_pk_max_f16 v1, s2, s2
+; GFX9-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX9-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX9-SDAG-NEXT: v_pk_min_f16 v0, v1, v0
+; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmin_v2f16_s_ieee_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_pk_max_f16 v0, s2, s2
+; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s3, s3
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: v_pk_min_f16 v0, v0, v1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmin_v2f16_s_ieee_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s3, s3
+; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, s2, s2
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, v1, v0
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmin_v2f16_s_ieee_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, s2, s2
+; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, s3, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
+ %val = call <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b)
+ store <2 x half> %val, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_ps <2 x half> @test_fmin_v2f16_s_ieee_off(<2 x half> inreg %a, <2 x half> inreg %b) #0 {
+; GFX8-SDAG-LABEL: test_fmin_v2f16_s_ieee_off:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_lshr_b32 s2, s1, 16
+; GFX8-SDAG-NEXT: s_lshr_b32 s3, s0, 16
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-SDAG-NEXT: v_min_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-SDAG-NEXT: v_min_f16_e32 v1, s0, v1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX8-GISEL-LABEL: test_fmin_v2f16_s_ieee_off:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-GISEL-NEXT: s_lshr_b32 s3, s1, 16
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, s0, v0
+; GFX8-GISEL-NEXT: s_lshr_b32 s2, s0, 16
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, s2, v0
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX8-GISEL-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX8-GISEL-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-GISEL-NEXT: s_lshl_b32 s1, s1, 16
+; GFX8-GISEL-NEXT: s_or_b32 s0, s0, s1
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-GISEL-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmin_v2f16_s_ieee_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_pk_min_f16 v0, s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmin_v2f16_s_ieee_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_pk_min_num_f16 v0, s0, s1
+; GFX12-NEXT: ; return to shader part epilog
+ %val = call <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b)
+ ret <2 x half> %val
+}
+
+define amdgpu_kernel void @test_fmin_f64_v_ieee_on(ptr addrspace(1) %out, double %a, double %b) #0 {
+; GFX8-SDAG-LABEL: test_fmin_f64_v_ieee_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_max_f64 v[0:1], s[6:7], s[6:7]
+; GFX8-SDAG-NEXT: v_max_f64 v[2:3], s[2:3], s[2:3]
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_min_f64 v[0:1], v[2:3], v[0:1]
+; GFX8-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmin_f64_v_ieee_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_max_f64 v[0:1], s[2:3], s[2:3]
+; GFX8-GISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX8-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmin_f64_v_ieee_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f64 v[0:1], s[6:7], s[6:7]
+; GFX9-SDAG-NEXT: v_max_f64 v[2:3], s[2:3], s[2:3]
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_min_f64 v[0:1], v[2:3], v[0:1]
+; GFX9-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmin_f64_v_ieee_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f64 v[0:1], s[2:3], s[2:3]
+; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[6:7], s[6:7]
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX9-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmin_f64_v_ieee_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[6:7], s[6:7]
+; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], s[2:3], s[2:3]
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmin_f64_v_ieee_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[2:3]
+; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[2:3], s[4:5], s[4:5]
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-GISEL-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
+ %val = call double @llvm.minnum.f64(double %a, double %b)
+ store double %val, ptr addrspace(1) %out, align 8
+ ret void
+}
+
+define amdgpu_ps double @test_fmin_f64_v_ieee_off(double %a, double %b) #0 {
+; GFX8-LABEL: test_fmin_f64_v_ieee_off:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmin_f64_v_ieee_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmin_f64_v_ieee_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: ; return to shader part epilog
+ %val = call double @llvm.minnum.f64(double %a, double %b)
+ ret double %val
+}
+
+define amdgpu_kernel void @test_fmin_f64_s_ieee_on(ptr addrspace(1) %out, double inreg %a, double inreg %b) #0 {
+; GFX8-SDAG-LABEL: test_fmin_f64_s_ieee_on:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_max_f64 v[2:3], s[2:3], s[2:3]
+; GFX8-SDAG-NEXT: v_max_f64 v[0:1], s[4:5], s[4:5]
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_min_f64 v[0:1], v[2:3], v[0:1]
+; GFX8-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: test_fmin_f64_s_ieee_on:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_max_f64 v[0:1], s[2:3], s[2:3]
+; GFX8-GISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX8-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: test_fmin_f64_s_ieee_on:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_max_f64 v[2:3], s[2:3], s[2:3]
+; GFX9-SDAG-NEXT: v_max_f64 v[0:1], s[6:7], s[6:7]
+; GFX9-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX9-SDAG-NEXT: v_min_f64 v[0:1], v[2:3], v[0:1]
+; GFX9-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: test_fmin_f64_s_ieee_on:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f64 v[0:1], s[2:3], s[2:3]
+; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[6:7], s[6:7]
+; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX9-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX12-SDAG-LABEL: test_fmin_f64_s_ieee_on:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[6:7], s[6:7]
+; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], s[2:3], s[2:3]
+; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: test_fmin_f64_s_ieee_on:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[2:3]
+; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[2:3], s[4:5], s[4:5]
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-GISEL-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX12-GISEL-NEXT: s_endpgm
+ %val = call double @llvm.minnum.f64(double %a, double %b)
+ store double %val, ptr addrspace(1) %out, align 8
+ ret void
+}
+
+define amdgpu_ps double @test_fmin_f64_s_ieee_off(double inreg %a, double inreg %b) #0 {
+; GFX8-LABEL: test_fmin_f64_s_ieee_off:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_min_f64 v[0:1], s[0:1], v[0:1]
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_fmin_f64_s_ieee_off:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_min_f64 v[0:1], s[0:1], v[0:1]
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: test_fmin_f64_s_ieee_off:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_min_num_f64_e64 v[0:1], s[0:1], s[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-NEXT: ; return to shader part epilog
+ %val = call double @llvm.minnum.f64(double %a, double %b)
+ ret double %val
+}
+
declare float @llvm.minnum.f32(float, float) #1
declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) #1
declare <3 x float> @llvm.minnum.v3f32(<3 x float>, <3 x float>) #1
declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1
declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>) #1
declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>) #1
+declare half @llvm.minnum.f16(half, half) #1
+declare double @llvm.minnum.f64(double, double) #1
+declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>) #1
attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
attributes #1 = { nounwind readnone }
More information about the llvm-commits
mailing list