[llvm] [DAG] isKnownToBeAPowerOfTwo - add DemandedElts + OrZero handling to … (PR #181753)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp --diff_from_common_commit
``````````

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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
index 1d1b21b91..82f4629a1 100644
--- a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
@@ -915,26 +915,24 @@ TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_Constants) {
   EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SplatBig, /*OrZero=*/true));
 
   auto Cond = DAG->getCopyFromReg(DAG->getEntryNode(), Loc, 1, MVT::i1);
-  auto Select40 = DAG->getNode(ISD::SELECT, Loc, MVT::i32,
-                               Cond, Cst4, Cst0);
-  auto Select43 = DAG->getNode(ISD::SELECT, Loc, MVT::i32,
-                               Cond, Cst4, Cst3);
-  auto Select4Big = DAG->getNode(ISD::SELECT, Loc, MVT::i32,
-                                 Cond, Cst4, CstBig);
+  auto Select40 = DAG->getNode(ISD::SELECT, Loc, MVT::i32, Cond, Cst4, Cst0);
+  auto Select43 = DAG->getNode(ISD::SELECT, Loc, MVT::i32, Cond, Cst4, Cst3);
+  auto Select4Big =
+      DAG->getNode(ISD::SELECT, Loc, MVT::i32, Cond, Cst4, CstBig);
   EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(Select40));
   EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(Select40, /*OrZero=*/true));
   EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(Select43));
   EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(Select4Big));
 
   auto VecCond = DAG->getCopyFromReg(DAG->getEntryNode(), Loc, 2, MVT::v2i1);
-  auto VSelect0444 = DAG->getNode(ISD::VSELECT, Loc, VecVT,
-                                  VecCond, Vec04, Vec44);
-  auto VSelect4444 = DAG->getNode(ISD::VSELECT, Loc, VecVT,
-                                  VecCond, Vec44, Vec44);
-  auto VSelect040Big = DAG->getNode(ISD::VSELECT, Loc, VecVT,
-                                    VecCond, Vec04, Vec0Big);
-  auto VSelect444Big = DAG->getNode(ISD::VSELECT, Loc, VecVT,
-                                    VecCond, Vec44, Vec4Big);
+  auto VSelect0444 =
+      DAG->getNode(ISD::VSELECT, Loc, VecVT, VecCond, Vec04, Vec44);
+  auto VSelect4444 =
+      DAG->getNode(ISD::VSELECT, Loc, VecVT, VecCond, Vec44, Vec44);
+  auto VSelect040Big =
+      DAG->getNode(ISD::VSELECT, Loc, VecVT, VecCond, Vec04, Vec0Big);
+  auto VSelect444Big =
+      DAG->getNode(ISD::VSELECT, Loc, VecVT, VecCond, Vec44, Vec4Big);
 
   EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(VSelect444Big, DemandHi));
   EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(VSelect444Big, DemandHi, true));

``````````

</details>


https://github.com/llvm/llvm-project/pull/181753