[llvm] [AArch64][GlobalISel] Use GPR for illegal fconstants and extend < 32 bit GPR constants to 32 bits (PR #178692)

[David Green via llvm-commits]

================
@@ -1,60 +1,122 @@
-; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-apple-darwin -global-isel | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck --check-prefixes=CHECK,CHECK-SD %s
+; RUN: llc < %s -mtriple=arm64-apple-darwin -global-isel | FileCheck --check-prefixes=CHECK,CHECK-GI %s
 
-; CHECK: literal8
-; CHECK: .quad  0x400921fb54442d18
 define double @foo() optsize {
-; CHECK: _foo:
-; CHECK: adrp x[[REG:[0-9]+]], lCPI0_0 at PAGE
-; CHECK: ldr  d0, [x[[REG]], lCPI0_0 at PAGEOFF]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: foo:
+; CHECK-SD:       ; %bb.0:
+; CHECK-SD-NEXT:  Lloh0:
+; CHECK-SD-NEXT:    adrp x8, lCPI0_0 at PAGE
+; CHECK-SD-NEXT:  Lloh1:
+; CHECK-SD-NEXT:    ldr d0, [x8, lCPI0_0 at PAGEOFF]
+; CHECK-SD-NEXT:    ret
+; CHECK-SD-NEXT:    .loh AdrpLdr Lloh0, Lloh1
+;
+; CHECK-GI-LABEL: foo:
+; CHECK-GI:       ; %bb.0:
+; CHECK-GI-NEXT:    mov x8, #11544 ; =0x2d18
+; CHECK-GI-NEXT:    movk x8, #21572, lsl #16
+; CHECK-GI-NEXT:    movk x8, #8699, lsl #32
+; CHECK-GI-NEXT:    movk x8, #16393, lsl #48
+; CHECK-GI-NEXT:    fmov d0, x8
+; CHECK-GI-NEXT:    ret
   ret double 0x400921FB54442D18
 }
 
-; CHECK: literal8
-; CHECK: .quad 0x0000001fffffffc
 define double @foo2() optsize {
-; CHECK: _foo2:
-; CHECK: adrp x[[REG:[0-9]+]], lCPI1_0 at PAGE
-; CHECK: ldr  d0, [x[[REG]], lCPI1_0 at PAGEOFF]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: foo2:
+; CHECK-SD:       ; %bb.0:
+; CHECK-SD-NEXT:  Lloh2:
+; CHECK-SD-NEXT:    adrp x8, lCPI1_0 at PAGE
+; CHECK-SD-NEXT:  Lloh3:
+; CHECK-SD-NEXT:    ldr d0, [x8, lCPI1_0 at PAGEOFF]
+; CHECK-SD-NEXT:    ret
+; CHECK-SD-NEXT:    .loh AdrpLdr Lloh2, Lloh3
+;
+; CHECK-GI-LABEL: foo2:
+; CHECK-GI:       ; %bb.0:
+; CHECK-GI-NEXT:    mov x8, #137438887936 ; =0x1fffff0000
+; CHECK-GI-NEXT:    movk x8, #65473
+; CHECK-GI-NEXT:    fmov d0, x8
+; CHECK-GI-NEXT:    ret
   ret double 0x1FFFFFFFC1
 }
 
 define float @bar() optsize {
-; CHECK: _bar:
-; CHECK: adrp x[[REG:[0-9]+]], lCPI2_0 at PAGE
-; CHECK: ldr  s0, [x[[REG]], lCPI2_0 at PAGEOFF]
-; CHECK-NEXT:  ret
+; CHECK-SD-LABEL: bar:
+; CHECK-SD:       ; %bb.0:
+; CHECK-SD-NEXT:  Lloh4:
+; CHECK-SD-NEXT:    adrp x8, lCPI2_0 at PAGE
+; CHECK-SD-NEXT:  Lloh5:
+; CHECK-SD-NEXT:    ldr s0, [x8, lCPI2_0 at PAGEOFF]
+; CHECK-SD-NEXT:    ret
+; CHECK-SD-NEXT:    .loh AdrpLdr Lloh4, Lloh5
+;
+; CHECK-GI-LABEL: bar:
+; CHECK-GI:       ; %bb.0:
+; CHECK-GI-NEXT:    mov w8, #4059 ; =0xfdb
+; CHECK-GI-NEXT:    movk w8, #16457, lsl #16
+; CHECK-GI-NEXT:    fmov s0, w8
+; CHECK-GI-NEXT:    ret
   ret float 0x400921FB60000000
 }
 
-; CHECK: literal16
-; CHECK: .quad 0
-; CHECK: .quad 0
 define fp128 @baz() optsize {
----------------
davemgreen wrote:

This should really be a fmov0

https://github.com/llvm/llvm-project/pull/178692