[llvm] c4e8adf - [VPlan] Skip gather/scatters in useEmulatedMaskMemRefHack.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 16 13:01:26 PST 2026
Author: Florian Hahn
Date: 2026-02-16T21:01:16Z
New Revision: c4e8adf7bbc8c1bcf2d3c8c808ca9a52677ce9c2
URL: https://github.com/llvm/llvm-project/commit/c4e8adf7bbc8c1bcf2d3c8c808ca9a52677ce9c2
DIFF: https://github.com/llvm/llvm-project/commit/c4e8adf7bbc8c1bcf2d3c8c808ca9a52677ce9c2.diff
LOG: [VPlan] Skip gather/scatters in useEmulatedMaskMemRefHack.
The legacy cost model skips gather/scatters when determining the
predicated stores in useEmulatedMaskMemRefHack. Match the behavior in
the VPlan-based implementation. This fixes a cost divergence in the
attached test.
Added:
Modified:
llvm/lib/Transforms/Vectorize/VPlan.cpp
llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp
index e4b05a410d303..f233f0dc1b025 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp
@@ -1824,6 +1824,8 @@ bool VPCostContext::useEmulatedMaskMemRefHack(const VPReplicateRecipe *R,
if (!NumPredStores) {
// Count the number of predicated stores in the VPlan, caching the result.
+ // Only stores where scatter is not legal are counted, matching the legacy
+ // cost model behavior.
const VPlan &Plan = *R->getParent()->getPlan();
NumPredStores = 0;
for (const VPRegionBlock *VPRB :
@@ -1833,10 +1835,20 @@ bool VPCostContext::useEmulatedMaskMemRefHack(const VPReplicateRecipe *R,
for (const VPBasicBlock *VPBB :
VPBlockUtils::blocksOnly<const VPBasicBlock>(
vp_depth_first_shallow(VPRB->getEntry()))) {
- *NumPredStores += count_if(*VPBB, [](const VPRecipeBase &R) {
- auto *RepR = dyn_cast<VPReplicateRecipe>(&R);
- return RepR && isa<StoreInst>(RepR->getUnderlyingInstr());
- });
+ for (const VPRecipeBase &Recipe : *VPBB) {
+ auto *RepR = dyn_cast<VPReplicateRecipe>(&Recipe);
+ if (!RepR)
+ continue;
+ if (!isa<StoreInst>(RepR->getUnderlyingInstr()))
+ continue;
+ // Check if scatter is legal for this store. If so, don't count it.
+ Type *Ty = Types.inferScalarType(RepR->getOperand(0));
+ auto *VTy = VectorType::get(Ty, VF);
+ const Align Alignment =
+ getLoadStoreAlignment(RepR->getUnderlyingInstr());
+ if (!TTI.isLegalMaskedScatter(VTy, Alignment))
+ ++(*NumPredStores);
+ }
}
}
}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll b/llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
index 41fb58c50ae00..eae8fc1e230e9 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
; RUN: opt -p loop-vectorize -S %s | FileCheck %s
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
@@ -155,3 +155,149 @@ exit:
%t.0.lcssa = phi i32 [ %t.0, %loop.latch ]
ret i32 %t.0.lcssa
}
+
+; Test case where scatter is legal (skylake-avx512) and stores are in predicated
+; blocks. The cost model should not apply the emulated mask hack for stores when
+; scatter is legal.
+define i32 @predicated_store_with_scatter_legal(ptr %dst, i64 %n) #0 {
+; CHECK-LABEL: define i32 @predicated_store_with_scatter_legal(
+; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 24
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
+; CHECK: [[VECTOR_SCEVCHECK]]:
+; CHECK-NEXT: [[MUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 36, i64 [[N]])
+; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i64, i1 } [[MUL]], 0
+; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i64, i1 } [[MUL]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[DST]], i64 [[MUL_RESULT]]
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult ptr [[TMP1]], [[DST]]
+; CHECK-NEXT: [[TMP3:%.*]] = or i1 [[TMP2]], [[MUL_OVERFLOW]]
+; CHECK-NEXT: br i1 [[TMP3]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 8
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE14:.*]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <8 x i64> [ <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE14]] ]
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr { i32, i32, [4 x i32], i32, i32, i32 }, ptr [[DST]], <8 x i64> [[VEC_IND]]
+; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> align 4 [[TMP4]], <8 x i1> splat (i1 true), <8 x i32> poison)
+; CHECK-NEXT: [[TMP5:%.*]] = shl <8 x i32> [[WIDE_MASKED_GATHER]], zeroinitializer
+; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i32> [[TMP5]] to <8 x i64>
+; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt <8 x i64> zeroinitializer, [[TMP6]]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i1> [[TMP7]], i32 0
+; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
+; CHECK: [[PRED_STORE_IF]]:
+; CHECK-NEXT: store i32 0, ptr null, align 4
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
+; CHECK: [[PRED_STORE_CONTINUE]]:
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i1> [[TMP7]], i32 1
+; CHECK-NEXT: br i1 [[TMP9]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]
+; CHECK: [[PRED_STORE_IF1]]:
+; CHECK-NEXT: store i32 0, ptr null, align 4
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE2]]
+; CHECK: [[PRED_STORE_CONTINUE2]]:
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i1> [[TMP7]], i32 2
+; CHECK-NEXT: br i1 [[TMP10]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]
+; CHECK: [[PRED_STORE_IF3]]:
+; CHECK-NEXT: store i32 0, ptr null, align 4
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]
+; CHECK: [[PRED_STORE_CONTINUE4]]:
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i1> [[TMP7]], i32 3
+; CHECK-NEXT: br i1 [[TMP11]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]
+; CHECK: [[PRED_STORE_IF5]]:
+; CHECK-NEXT: store i32 0, ptr null, align 4
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]
+; CHECK: [[PRED_STORE_CONTINUE6]]:
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <8 x i1> [[TMP7]], i32 4
+; CHECK-NEXT: br i1 [[TMP12]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]
+; CHECK: [[PRED_STORE_IF7]]:
+; CHECK-NEXT: store i32 0, ptr null, align 4
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE8]]
+; CHECK: [[PRED_STORE_CONTINUE8]]:
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <8 x i1> [[TMP7]], i32 5
+; CHECK-NEXT: br i1 [[TMP13]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]
+; CHECK: [[PRED_STORE_IF9]]:
+; CHECK-NEXT: store i32 0, ptr null, align 4
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE10]]
+; CHECK: [[PRED_STORE_CONTINUE10]]:
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <8 x i1> [[TMP7]], i32 6
+; CHECK-NEXT: br i1 [[TMP14]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]]
+; CHECK: [[PRED_STORE_IF11]]:
+; CHECK-NEXT: store i32 0, ptr null, align 4
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE12]]
+; CHECK: [[PRED_STORE_CONTINUE12]]:
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <8 x i1> [[TMP7]], i32 7
+; CHECK-NEXT: br i1 [[TMP15]], label %[[PRED_STORE_IF13:.*]], label %[[PRED_STORE_CONTINUE14]]
+; CHECK: [[PRED_STORE_IF13]]:
+; CHECK-NEXT: store i32 0, ptr null, align 4
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE14]]
+; CHECK: [[PRED_STORE_CONTINUE14]]:
+; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> zeroinitializer, <8 x ptr> align 4 [[TMP4]], <8 x i1> zeroinitializer)
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <8 x i64> [[VEC_IND]], splat (i64 8)
+; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[LOOP]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; CHECK-NEXT: br label %[[LOOP1:.*]]
+; CHECK: [[LOOP1]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr { i32, i32, [4 x i32], i32, i32, i32 }, ptr [[DST]], i64 [[IV]]
+; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP]], align 4
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[L]], 0
+; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[SHL]] to i64
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i64 0, [[SEXT]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[LATCH]]
+; CHECK: [[IF_THEN]]:
+; CHECK-NEXT: br i1 false, label %[[IF_ELSE:.*]], label %[[IF_THEN2:.*]]
+; CHECK: [[IF_THEN2]]:
+; CHECK-NEXT: store i32 0, ptr null, align 4
+; CHECK-NEXT: br label %[[LATCH]]
+; CHECK: [[IF_ELSE]]:
+; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4
+; CHECK-NEXT: br label %[[LATCH]]
+; CHECK: [[LATCH]]:
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP1]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret i32 0
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ]
+ %gep = getelementptr { i32, i32, [4 x i32], i32, i32, i32 }, ptr %dst, i64 %iv
+ %l = load i32, ptr %gep, align 4
+ %shl = shl i32 %l, 0
+ %sext = sext i32 %shl to i64
+ %cmp = icmp sgt i64 0, %sext
+ br i1 %cmp, label %if.then, label %latch
+
+if.then:
+ br i1 false, label %if.else, label %if.then2
+
+if.then2:
+ store i32 0, ptr null, align 4
+ br label %latch
+
+if.else:
+ store i32 0, ptr %gep, align 4
+ br label %latch
+
+latch:
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv, %n
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret i32 0
+}
+
+attributes #0 = { "target-cpu"="skylake-avx512" }
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