[llvm] [AArch64] Prefer SVE2 for fixed-length i64 [S|U][MIN|MAX] reductions (PR #181161)

[Benjamin Maxwell via llvm-commits]

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@@ -31577,12 +31536,31 @@ SDValue AArch64TargetLowering::LowerReductionToSVE(unsigned Opcode,
   // UADDV always returns an i64 result.
   EVT ResVT = (Opcode == AArch64ISD::UADDV_PRED) ? MVT::i64 :
                                                    SrcVT.getVectorElementType();
+
+  SDValue Rdx;
+  // Lower v2<ty> VECREDUCE_[US](MIN|MAX) to pairwise operation with SVE2/SME.
+  if (SrcVT.getVectorElementCount() == ElementCount::getFixed(2) &&
+      (Subtarget->hasSVE2() || Subtarget->hasSME())) {
+    if (std::optional<Intrinsic::ID> PairwiseIID =
+            getPairwiseOpForReduction(ScalarOp->getOpcode())) {
+      EVT VT = VecOp.getValueType();
+      EVT PredVT = VT.changeVectorElementType(*DAG.getContext(), MVT::i1);
+      // VL1 as the pairwise operations use two input lanes per one output lane.
+      SDValue PTrueVL1 = getPTrue(DAG, DL, PredVT, AArch64SVEPredPattern::vl1);
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MacDue wrote:

Sure, that works. Using `vl1` here was a little pedantic :+1: 

https://github.com/llvm/llvm-project/pull/181161