[llvm] [TableGen] Use a new helper function for -register-info-debug. NFC. (PR #181704)

[Jay Foad via llvm-commits]

https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/181704

Use a new helper function for printing things derived from InfoByHwMode.


>From 8d7d73f437e66591607935590f17556417ce1bb7 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Mon, 16 Feb 2026 16:55:09 +0000
Subject: [PATCH] [TableGen] Use a new helper function for
 -register-info-debug. NFC.

Use a new helper function for printing things derived from InfoByHwMode.
---
 llvm/utils/TableGen/RegisterInfoEmitter.cpp | 55 ++++++++++++---------
 1 file changed, 33 insertions(+), 22 deletions(-)

diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 3df439d681e8a..04b9e6112925c 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -29,6 +29,7 @@
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Format.h"
+#include "llvm/Support/Printable.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/TableGen/CodeGenHelpers.h"
 #include "llvm/TableGen/Error.h"
@@ -86,6 +87,9 @@ class RegisterInfoEmitter {
   // run - Output the register file description.
   TableGenOutputFiles run(StringRef FilenamePrefix);
 
+  template <typename InfoTy, typename FnTy>
+  Printable printByHwMode(const InfoByHwMode<InfoTy> &Info, FnTy Func);
+
   void debugDump(raw_ostream &OS);
 
 private:
@@ -1877,24 +1881,32 @@ TableGenOutputFiles RegisterInfoEmitter::run(StringRef FilenamePrefix) {
            {"TargetDesc.inc", TargetDesc}}};
 }
 
-void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
-  const CodeGenHwModes &CGH = Target.getHwModes();
-  unsigned NumModes = CGH.getNumModeIds();
-  auto getModeName = [CGH](unsigned M) -> StringRef {
-    if (M == 0)
-      return "Default";
-    return CGH.getMode(M).Name;
-  };
+template <typename InfoTy, typename FnTy>
+Printable RegisterInfoEmitter::printByHwMode(const InfoByHwMode<InfoTy> &Info,
+                                             FnTy Func) {
+  return Printable([&](raw_ostream &OS) {
+    const CodeGenHwModes &CGH = Target.getHwModes();
+
+    OS << "{";
+    for (unsigned M = 0, E = CGH.getNumModeIds(); M != E; ++M)
+      OS << ' ' << (M ? CGH.getModeName(M, true) : "Default") << ':'
+         << Func(Info.get(M));
+    OS << " }";
+  });
+}
 
+void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
   for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) {
     OS << "RegisterClass " << RC.getName() << ":\n";
-    OS << "\tSpillSize: {";
-    for (unsigned M = 0; M != NumModes; ++M)
-      OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize;
-    OS << " }\n\tSpillAlignment: {";
-    for (unsigned M = 0; M != NumModes; ++M)
-      OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment;
-    OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n';
+    OS << "\tSpillSize: " << printByHwMode(RC.RSI, [](const RegSizeInfo &Info) {
+      return Info.SpillSize;
+    }) << '\n';
+    OS << "\tSpillAlignment: "
+       << printByHwMode(
+              RC.RSI,
+              [](const RegSizeInfo &Info) { return Info.SpillAlignment; })
+       << '\n';
+    OS << "\tNumRegs: " << RC.getMembers().size() << '\n';
     OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n';
     OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n';
     OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n';
@@ -1925,13 +1937,12 @@ void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
     OS << "SubRegIndex " << SRI.getName() << ":\n";
     OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n';
     OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n';
-    OS << "\tOffset: {";
-    for (unsigned M = 0; M != NumModes; ++M)
-      OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Offset;
-    OS << " }\n\tSize: {";
-    for (unsigned M = 0; M != NumModes; ++M)
-      OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Size;
-    OS << " }\n";
+    OS << "\tOffset: " << printByHwMode(SRI.Range, [](const SubRegRange &Info) {
+      return Info.Offset;
+    }) << '\n';
+    OS << "\tSize: " << printByHwMode(SRI.Range, [](const SubRegRange &Info) {
+      return Info.Size;
+    }) << '\n';
   }
 
   for (const CodeGenRegister &R : RegBank.getRegisters()) {