[llvm] [AArch64] Prefer SVE2 for fixed-length i64 [S|U][MIN|MAX] reductions (PR #181161)

[Paul Walker via llvm-commits]

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@@ -708,21 +633,36 @@ entry:
 }
 
 define i64 @sminv_v3i64(<3 x i64> %a) {
-; CHECK-SD-LABEL: sminv_v3i64:
-; CHECK-SD:       // %bb.0: // %entry
-; CHECK-SD-NEXT:    // kill: def $d2 killed $d2 def $q2
-; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT:    mov x8, #9223372036854775807 // =0x7fffffffffffffff
-; CHECK-SD-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-SD-NEXT:    mov v0.d[1], v1.d[0]
-; CHECK-SD-NEXT:    mov v2.d[1], x8
-; CHECK-SD-NEXT:    cmgt v1.2d, v2.2d, v0.2d
-; CHECK-SD-NEXT:    bif v0.16b, v2.16b, v1.16b
-; CHECK-SD-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT:    cmgt d2, d1, d0
-; CHECK-SD-NEXT:    bif v0.8b, v1.8b, v2.8b
-; CHECK-SD-NEXT:    fmov x0, d0
-; CHECK-SD-NEXT:    ret
+; CHECK-SD-NOSVE-LABEL: sminv_v3i64:
+; CHECK-SD-NOSVE:       // %bb.0: // %entry
+; CHECK-SD-NOSVE-NEXT:    // kill: def $d2 killed $d2 def $q2
+; CHECK-SD-NOSVE-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NOSVE-NEXT:    mov x8, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-SD-NOSVE-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-SD-NOSVE-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-SD-NOSVE-NEXT:    mov v2.d[1], x8
+; CHECK-SD-NOSVE-NEXT:    cmgt v1.2d, v2.2d, v0.2d
+; CHECK-SD-NOSVE-NEXT:    bif v0.16b, v2.16b, v1.16b
+; CHECK-SD-NOSVE-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT:    cmgt d2, d1, d0
+; CHECK-SD-NOSVE-NEXT:    bif v0.8b, v1.8b, v2.8b
+; CHECK-SD-NOSVE-NEXT:    fmov x0, d0
+; CHECK-SD-NOSVE-NEXT:    ret
+;
+; CHECK-SD-SVE2-LABEL: sminv_v3i64:
+; CHECK-SD-SVE2:       // %bb.0: // %entry
+; CHECK-SD-SVE2-NEXT:    // kill: def $d2 killed $d2 def $z2
+; CHECK-SD-SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; CHECK-SD-SVE2-NEXT:    mov x8, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-SD-SVE2-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-SD-SVE2-NEXT:    ptrue p0.d, vl2
+; CHECK-SD-SVE2-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-SD-SVE2-NEXT:    mov v2.d[1], x8
+; CHECK-SD-SVE2-NEXT:    smin z0.d, p0/m, z0.d, z2.d
+; CHECK-SD-SVE2-NEXT:    ptrue p0.d, vl1
----------------
paulwalker-arm wrote:

Wasn't expecting to see it here but this is an example of what I mentioned above.  For sequences of v2i64 lowered nodes it would be nicer to use a single predicate throughout if possible.

https://github.com/llvm/llvm-project/pull/181161