[llvm] [GlobalISel] Add sub_one_from_sub from SelectionDAG (PR #181670)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-globalisel

Author: Osman Yasar (osmanyasar05)

<details>
<summary>Changes</summary>

This PR adds the rewrite `// fold (A - B) - 1  ->  add (xor B, -1), A` from [SelectionDAG](https://github.com/llvm/llvm-project/blob/3765b09d20e01976a6ab6f8b922a6b93751fbf44/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L4411) to GlobalISel.

---
Full diff: https://github.com/llvm/llvm-project/pull/181670.diff


2 Files Affected:

- (modified) llvm/include/llvm/Target/GlobalISel/Combine.td (+9-1) 
- (added) llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir (+23) 


``````````diff
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index f5c940bffc8fb..5972bcffcd5ac 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -578,6 +578,14 @@ def right_identity_one_int: GICombineRule<
   (apply (GIReplaceReg $dst, $x))
 >;
 
+// fold (A - B) - 1  ->  add (xor B, -1), A
+def sub_one_from_sub: GICombineRule<
+  (defs root:$dst),
+  (match (G_SUB $sub1, $a, $b),
+         (G_SUB $dst, $sub1, 1)),
+  (apply (G_XOR $xor1, $b, -1),
+         (G_ADD $dst, $xor1, $a))>;
+
 def right_identity_one_fp: GICombineRule<
   (defs root:$dst),
   (match (G_FMUL $dst, $x, $y):$root,
@@ -2296,7 +2304,7 @@ def all_combines : GICombineGroup<[integer_reassoc_combines, trivial_combines,
     simplify_neg_minmax, combine_concat_vector,
     sext_trunc, zext_trunc, prefer_sign_combines, shuffle_combines,
     combine_use_vector_truncate, merge_combines, overflow_combines, 
-    truncsat_combines, lshr_of_trunc_of_lshr, ctls_combines, add_shift]>;
+    truncsat_combines, lshr_of_trunc_of_lshr, ctls_combines, add_shift, sub_one_from_sub]>;
 
 // A combine group used to for prelegalizer combiners at -O0. The combines in
 // this group have been selected based on experiments to balance code size and
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
new file mode 100644
index 0000000000000..47a74c465beb7
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
@@ -0,0 +1,23 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+---
+name: sub_one_from_sub
+body:             |
+  bb.1:
+  liveins: $w0, $w1
+
+    ; CHECK-LABEL: name: sub_one_from_sub
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C]]
+    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[XOR]], [[COPY]]
+    ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
+    %0:_(s32) = COPY $w0
+    %1:_(s32) = COPY $w1
+    %cst:_(s32) = G_CONSTANT i32 1
+    %2:_(s32) = G_SUB %0, %1
+    %3:_(s32) = G_SUB %2, %cst
+    $w0 = COPY %3(s32)

``````````

</details>


https://github.com/llvm/llvm-project/pull/181670