[llvm] [AArch64] Wrap integer SCALAR_TO_VECTOR nodes in bitcasts (PR #172837)

[via llvm-commits]

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@@ -537,6 +538,29 @@ char AArch64DAGToDAGISelLegacy::ID = 0;
 
 INITIALIZE_PASS(AArch64DAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
 
+/// addBitcastHints - This method adds bitcast hints to the operands of a node
+/// to help instruction selector determine which operands are in Neon registers.
+static SDValue addBitcastHints(SelectionDAG &DAG, SDNode &N) {
+  SDLoc DL(&N);
+  auto getFloatVT = [&](EVT VT) {
+    EVT ScalarVT = VT.getScalarType();
+    assert((ScalarVT == MVT::i32 || ScalarVT == MVT::i64) && "Unexpected VT");
+    return VT.changeElementType(*(DAG.getContext()),
+                                ScalarVT == MVT::i32 ? MVT::f32 : MVT::f64);
+  };
+  auto bitcastToFloat = [&](SDValue Val) {
+    return DAG.getBitcast(getFloatVT(Val.getValueType()), Val);
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Lukacma wrote:

That would skip the first operand which is incorrect. I have fixed the reserve though. That one was also missing space for the extra operand

https://github.com/llvm/llvm-project/pull/172837