[llvm] 2380e12 - [RISCV] Start zvlsseg-spill.mir test before regalloc. NFC

[Luke Lau via llvm-commits]

Author: Luke Lau
Date: 2026-02-16T16:10:54+08:00
New Revision: 2380e12fd61b687b82a1a67cb0161c9d6a77f4f6

URL: https://github.com/llvm/llvm-project/commit/2380e12fd61b687b82a1a67cb0161c9d6a77f4f6
DIFF: https://github.com/llvm/llvm-project/commit/2380e12fd61b687b82a1a67cb0161c9d6a77f4f6.diff

LOG: [RISCV] Start zvlsseg-spill.mir test before regalloc. NFC

Currently this starts from the beginning of the codegen pipeline, but
because it has pseudos that directly define physical registers this
triggers an assertion in an upcoming change to RISCVVLOptimizer. In the
full pipeline a vector pseudo should only define virtual VR registers.

Move it to before regalloc to avoid the crash. It could probably be
moved further to just before prologepilog but we would need to change
the input to handle vsetvli insertion too.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
index 8b4adac06716e..cc9cdb45ad6ff 100644
--- a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+v -start-before=greedy -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
 
 --- |
   define void @zvlsseg_spill_0(ptr %base, i64 %vl) {