[llvm] [AMDGPU] Teach SIPreEmitPeephole pass to preserve MachineLoopInfo (PR #178868)
Dark Steve via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 15 23:51:21 PST 2026
https://github.com/PrasoonMishra updated https://github.com/llvm/llvm-project/pull/178868
>From 9f119d890c71feb057fb221ff36ba090b2b2c550 Mon Sep 17 00:00:00 2001
From: Prasoon Mishra <Prasoon.Mishra at amd.com>
Date: Fri, 30 Jan 2026 08:14:30 +0000
Subject: [PATCH 1/7] Preserve MLI info in SIPreEmitPeephole.
---
llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp | 21 ++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
index 3edc98f21a074..618ba58779eaf 100644
--- a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
@@ -24,6 +24,7 @@
#include "llvm/ADT/SetVector.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/Support/BranchProbability.h"
@@ -37,8 +38,9 @@ class SIPreEmitPeephole {
private:
const SIInstrInfo *TII = nullptr;
const SIRegisterInfo *TRI = nullptr;
+ bool CFGModified = false;
- bool optimizeVccBranch(MachineInstr &MI) const;
+ bool optimizeVccBranch(MachineInstr &MI);
bool optimizeSetGPR(MachineInstr &First, MachineInstr &MI) const;
bool getBlockDestinations(MachineBasicBlock &SrcMBB,
MachineBasicBlock *&TrueMBB,
@@ -79,6 +81,7 @@ class SIPreEmitPeephole {
public:
bool run(MachineFunction &MF);
+ bool isCFGModified() const { return CFGModified; }
};
class SIPreEmitPeepholeLegacy : public MachineFunctionPass {
@@ -101,7 +104,7 @@ char SIPreEmitPeepholeLegacy::ID = 0;
char &llvm::SIPreEmitPeepholeID = SIPreEmitPeepholeLegacy::ID;
-bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const {
+bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) {
// Match:
// sreg = -1 or 0
// vcc = S_AND_B64 exec, sreg or S_ANDN2_B64 exec, sreg
@@ -226,6 +229,7 @@ bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const {
bool IsVCCZ = MI.getOpcode() == AMDGPU::S_CBRANCH_VCCZ;
if (SReg == ExecReg) {
+ CFGModified = true;
// EXEC is updated directly
if (IsVCCZ) {
MI.eraseFromParent();
@@ -233,6 +237,7 @@ bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const {
}
MI.setDesc(TII->get(AMDGPU::S_BRANCH));
} else if (IsVCCZ && MaskValue == 0) {
+ CFGModified = true;
// Will always branch
// Remove all successors shadowed by new unconditional branch
MachineBasicBlock *Parent = MI.getParent();
@@ -262,6 +267,7 @@ bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const {
MI.setDesc(TII->get(AMDGPU::S_BRANCH));
} else if (!IsVCCZ && MaskValue == 0) {
// Will never branch
+ CFGModified = true;
MachineOperand &Dst = MI.getOperand(0);
assert(Dst.isMBB() && "destination is not basic block");
MI.getParent()->removeSuccessor(Dst.getMBB());
@@ -447,6 +453,7 @@ bool SIPreEmitPeephole::removeExeczBranch(MachineInstr &MI,
LLVM_DEBUG(dbgs() << "Removing the execz branch: " << MI);
MI.eraseFromParent();
SrcMBB.removeSuccessor(TrueMBB);
+ CFGModified = true;
return true;
}
@@ -707,9 +714,14 @@ llvm::SIPreEmitPeepholePass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM) {
auto *MDT = MFAM.getCachedResult<MachineDominatorTreeAnalysis>(MF);
auto *MPDT = MFAM.getCachedResult<MachinePostDominatorTreeAnalysis>(MF);
+ SIPreEmitPeephole Impl;
- if (SIPreEmitPeephole().run(MF))
- return getMachineFunctionPassPreservedAnalyses();
+ if (Impl.run(MF)) {
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ if (!Impl.isCFGModified())
+ PA.preserve<MachineLoopAnalysis>();
+ return PA;
+ }
if (MDT)
MDT->updateBlockNumbers();
@@ -722,6 +734,7 @@ bool SIPreEmitPeephole::run(MachineFunction &MF) {
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
TII = ST.getInstrInfo();
TRI = &TII->getRegisterInfo();
+ CFGModified = false;
bool Changed = false;
MF.RenumberBlocks();
>From de936d4add32f05bda14095dd41be18edb30b7b9 Mon Sep 17 00:00:00 2001
From: Prasoon Mishra <Prasoon.Mishra at amd.com>
Date: Fri, 30 Jan 2026 09:34:35 +0000
Subject: [PATCH 2/7] Add test.
---
...i-pre-emit-peephole-preserve-loop-info.mir | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-emit-peephole-preserve-loop-info.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-emit-peephole-preserve-loop-info.mir b/llvm/test/CodeGen/AMDGPU/si-pre-emit-peephole-preserve-loop-info.mir
new file mode 100644
index 0000000000000..4347117f7dc94
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-emit-peephole-preserve-loop-info.mir
@@ -0,0 +1,27 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes="require<machine-loops>,si-pre-emit-peephole,print<machine-loops>" -debug-pass-manager -filetype=null %s 2>&1 | FileCheck %s
+
+# CHECK: Running analysis: MachineLoopAnalysis on vcc_and_removal_preserves_mli
+# CHECK-NEXT: Running analysis: MachineDominatorTreeAnalysis on vcc_and_removal_preserves_mli
+# CHECK-NEXT: Running pass: SIPreEmitPeepholePass on vcc_and_removal_preserves_mli
+# CHECK-NEXT: Invalidating analysis: MachineDominatorTreeAnalysis on vcc_and_removal_preserves_mli
+# CHECK-NEXT: Running pass: MachineLoopPrinterPass on vcc_and_removal_preserves_mli
+# CHECK-NEXT: Machine loop info for machine function 'vcc_and_removal_preserves_mli':
+# CHECK-NOT: Running analysis: MachineLoopAnalysis on vcc_and_removal_preserves_mli
+# CHECK-NEXT: Loop at depth 1 containing: %bb.1<header><latch><exiting>
+
+---
+name: vcc_and_removal_preserves_mli
+body: |
+ bb.0:
+ S_BRANCH %bb.1
+
+ ; S_AND gets removed
+ bb.1:
+ V_CMP_EQ_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec
+ $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
+ S_CBRANCH_VCCNZ %bb.1, implicit $vcc
+ S_BRANCH %bb.2
+
+ bb.2:
+ S_ENDPGM 0
+...
>From f820d40370f895f4dbf9b3b9cd200f20f7439d54 Mon Sep 17 00:00:00 2001
From: Dark Steve <Prasoon.Mishra at amd.com>
Date: Wed, 11 Feb 2026 07:53:58 +0000
Subject: [PATCH 3/7] Preserve MLI by restricting cfg optimization in loops.
---
llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp | 40 ++++++++++++--------
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
index 618ba58779eaf..95810d4fe4f90 100644
--- a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
@@ -38,9 +38,9 @@ class SIPreEmitPeephole {
private:
const SIInstrInfo *TII = nullptr;
const SIRegisterInfo *TRI = nullptr;
- bool CFGModified = false;
+ MachineLoopInfo *MLI = nullptr;
- bool optimizeVccBranch(MachineInstr &MI);
+ bool optimizeVccBranch(MachineInstr &MI) const;
bool optimizeSetGPR(MachineInstr &First, MachineInstr &MI) const;
bool getBlockDestinations(MachineBasicBlock &SrcMBB,
MachineBasicBlock *&TrueMBB,
@@ -80,8 +80,7 @@ class SIPreEmitPeephole {
bool IsHiBits, const MachineOperand &SrcMO);
public:
- bool run(MachineFunction &MF);
- bool isCFGModified() const { return CFGModified; }
+ bool run(MachineFunction &MF, MachineLoopInfo *MLI);
};
class SIPreEmitPeepholeLegacy : public MachineFunctionPass {
@@ -90,8 +89,16 @@ class SIPreEmitPeepholeLegacy : public MachineFunctionPass {
SIPreEmitPeepholeLegacy() : MachineFunctionPass(ID) {}
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.addUsedIfAvailable<MachineLoopInfoWrapperPass>();
+ AU.addPreserved<MachineLoopInfoWrapperPass>();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
bool runOnMachineFunction(MachineFunction &MF) override {
- return SIPreEmitPeephole().run(MF);
+ auto *MLIWrapper = getAnalysisIfAvailable<MachineLoopInfoWrapperPass>();
+ MachineLoopInfo *MLI = MLIWrapper ? &MLIWrapper->getLI() : nullptr;
+ return SIPreEmitPeephole().run(MF, MLI);
}
};
@@ -104,7 +111,7 @@ char SIPreEmitPeepholeLegacy::ID = 0;
char &llvm::SIPreEmitPeepholeID = SIPreEmitPeepholeLegacy::ID;
-bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) {
+bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const {
// Match:
// sreg = -1 or 0
// vcc = S_AND_B64 exec, sreg or S_ANDN2_B64 exec, sreg
@@ -228,8 +235,14 @@ bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) {
}
bool IsVCCZ = MI.getOpcode() == AMDGPU::S_CBRANCH_VCCZ;
+
+ // Skip CFG-modifying VCC branch optimizations in loop bodies to preserve
+ // MachineLoopInfo.
+ if (MLI && MLI->getLoopFor(MI.getParent()) &&
+ (SReg == ExecReg || MaskValue == 0))
+ return Changed;
+
if (SReg == ExecReg) {
- CFGModified = true;
// EXEC is updated directly
if (IsVCCZ) {
MI.eraseFromParent();
@@ -237,7 +250,6 @@ bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) {
}
MI.setDesc(TII->get(AMDGPU::S_BRANCH));
} else if (IsVCCZ && MaskValue == 0) {
- CFGModified = true;
// Will always branch
// Remove all successors shadowed by new unconditional branch
MachineBasicBlock *Parent = MI.getParent();
@@ -267,7 +279,6 @@ bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) {
MI.setDesc(TII->get(AMDGPU::S_BRANCH));
} else if (!IsVCCZ && MaskValue == 0) {
// Will never branch
- CFGModified = true;
MachineOperand &Dst = MI.getOperand(0);
assert(Dst.isMBB() && "destination is not basic block");
MI.getParent()->removeSuccessor(Dst.getMBB());
@@ -453,7 +464,6 @@ bool SIPreEmitPeephole::removeExeczBranch(MachineInstr &MI,
LLVM_DEBUG(dbgs() << "Removing the execz branch: " << MI);
MI.eraseFromParent();
SrcMBB.removeSuccessor(TrueMBB);
- CFGModified = true;
return true;
}
@@ -714,12 +724,12 @@ llvm::SIPreEmitPeepholePass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM) {
auto *MDT = MFAM.getCachedResult<MachineDominatorTreeAnalysis>(MF);
auto *MPDT = MFAM.getCachedResult<MachinePostDominatorTreeAnalysis>(MF);
+ auto *MLI = MFAM.getCachedResult<MachineLoopAnalysis>(MF);
SIPreEmitPeephole Impl;
- if (Impl.run(MF)) {
+ if (Impl.run(MF, MLI)) {
auto PA = getMachineFunctionPassPreservedAnalyses();
- if (!Impl.isCFGModified())
- PA.preserve<MachineLoopAnalysis>();
+ PA.preserve<MachineLoopAnalysis>();
return PA;
}
@@ -730,11 +740,11 @@ llvm::SIPreEmitPeepholePass::run(MachineFunction &MF,
return PreservedAnalyses::all();
}
-bool SIPreEmitPeephole::run(MachineFunction &MF) {
+bool SIPreEmitPeephole::run(MachineFunction &MF, MachineLoopInfo *LoopInfo) {
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
TII = ST.getInstrInfo();
TRI = &TII->getRegisterInfo();
- CFGModified = false;
+ MLI = LoopInfo;
bool Changed = false;
MF.RenumberBlocks();
>From 84132c50476def914ca8cbf2b898f5e1e4b1f08a Mon Sep 17 00:00:00 2001
From: Dark Steve <Prasoon.Mishra at amd.com>
Date: Wed, 11 Feb 2026 11:45:54 +0000
Subject: [PATCH 4/7] Updating MLI incrementally, so that all opt can fire.
---
llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp | 58 +++++++++++++++++---
1 file changed, 51 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
index 95810d4fe4f90..ad1ef6dbfd52c 100644
--- a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
@@ -41,6 +41,8 @@ class SIPreEmitPeephole {
MachineLoopInfo *MLI = nullptr;
bool optimizeVccBranch(MachineInstr &MI) const;
+ void updateMLIBeforeRemovingEdge(MachineBasicBlock *From,
+ MachineBasicBlock *To) const;
bool optimizeSetGPR(MachineInstr &First, MachineInstr &MI) const;
bool getBlockDestinations(MachineBasicBlock &SrcMBB,
MachineBasicBlock *&TrueMBB,
@@ -111,6 +113,50 @@ char SIPreEmitPeepholeLegacy::ID = 0;
char &llvm::SIPreEmitPeepholeID = SIPreEmitPeepholeLegacy::ID;
+void SIPreEmitPeephole::updateMLIBeforeRemovingEdge(
+ MachineBasicBlock *From, MachineBasicBlock *To) const {
+ if (!MLI)
+ return;
+
+ // Only handle back-edges: To must be a loop header with From inside the loop.
+ MachineLoop *Loop = MLI->getLoopFor(To);
+ if (!Loop || Loop->getHeader() != To || !Loop->contains(From))
+ return;
+
+ // Count back-edges
+ unsigned BackEdgeCount = 0;
+ for (MachineBasicBlock *Pred : To->predecessors()) {
+ if (Loop->contains(Pred))
+ BackEdgeCount++;
+ }
+
+ if (BackEdgeCount <= 1) {
+ MachineLoop *ParentLoop = Loop->getParentLoop();
+
+ // Re-map blocks directly owned by this loop to the parent.
+ for (MachineBasicBlock *BB : Loop->blocks()) {
+ if (MLI->getLoopFor(BB) == Loop)
+ MLI->changeLoopFor(BB, ParentLoop);
+ }
+
+ // Reparent all child loops.
+ while (!Loop->isInnermost()) {
+ MachineLoop *Child = Loop->removeChildLoop(std::prev(Loop->end()));
+ if (ParentLoop)
+ ParentLoop->addChildLoop(Child);
+ else
+ MLI->addTopLevelLoop(Child);
+ }
+
+ if (ParentLoop)
+ ParentLoop->removeChildLoop(Loop);
+ else
+ MLI->removeLoop(llvm::find(*MLI, Loop));
+
+ MLI->destroy(Loop);
+ }
+}
+
bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const {
// Match:
// sreg = -1 or 0
@@ -236,12 +282,6 @@ bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const {
bool IsVCCZ = MI.getOpcode() == AMDGPU::S_CBRANCH_VCCZ;
- // Skip CFG-modifying VCC branch optimizations in loop bodies to preserve
- // MachineLoopInfo.
- if (MLI && MLI->getLoopFor(MI.getParent()) &&
- (SReg == ExecReg || MaskValue == 0))
- return Changed;
-
if (SReg == ExecReg) {
// EXEC is updated directly
if (IsVCCZ) {
@@ -267,11 +307,13 @@ bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const {
for (auto *BranchMI : ToRemove) {
MachineOperand &Dst = BranchMI->getOperand(0);
assert(Dst.isMBB() && "destination is not basic block");
+ updateMLIBeforeRemovingEdge(Parent, Dst.getMBB());
Parent->removeSuccessor(Dst.getMBB());
BranchMI->eraseFromParent();
}
if (MachineBasicBlock *Succ = Parent->getFallThrough()) {
+ updateMLIBeforeRemovingEdge(Parent, Succ);
Parent->removeSuccessor(Succ);
}
@@ -281,7 +323,9 @@ bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const {
// Will never branch
MachineOperand &Dst = MI.getOperand(0);
assert(Dst.isMBB() && "destination is not basic block");
- MI.getParent()->removeSuccessor(Dst.getMBB());
+ MachineBasicBlock *Parent = MI.getParent();
+ updateMLIBeforeRemovingEdge(Parent, Dst.getMBB());
+ Parent->removeSuccessor(Dst.getMBB());
MI.eraseFromParent();
return true;
} else if (MaskValue == -1) {
>From b3ad45833ddf981b3cb2399a53c8f2dd894f4ba8 Mon Sep 17 00:00:00 2001
From: Dark Steve <Prasoon.Mishra at amd.com>
Date: Wed, 11 Feb 2026 14:09:22 +0000
Subject: [PATCH 5/7] Add one more test.
---
...i-pre-emit-peephole-preserve-loop-info.mir | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-emit-peephole-preserve-loop-info.mir b/llvm/test/CodeGen/AMDGPU/si-pre-emit-peephole-preserve-loop-info.mir
index 4347117f7dc94..e3ac9f70a50a0 100644
--- a/llvm/test/CodeGen/AMDGPU/si-pre-emit-peephole-preserve-loop-info.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-emit-peephole-preserve-loop-info.mir
@@ -25,3 +25,28 @@ body: |
bb.2:
S_ENDPGM 0
...
+
+# CHECK-LABEL: Running pass: SIPreEmitPeepholePass on vcc_branch_destroys_loop
+# CHECK-NOT: Running analysis: MachineLoopAnalysis on vcc_branch_destroys_loop
+# CHECK: Machine loop info for machine function 'vcc_branch_destroys_loop':
+# CHECK-NOT: Loop at depth
+
+---
+name: vcc_branch_destroys_loop
+body: |
+ bb.0:
+ S_BRANCH %bb.1
+
+ ; After opt, S_CBRANCH_VCCZ becomes S_BRANCH %bb.3, S_BRANCH %bb.1 removed.
+ bb.1:
+ $vcc = S_MOV_B64 0
+ $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
+ S_CBRANCH_VCCZ %bb.3, implicit $vcc
+ S_BRANCH %bb.1
+
+ bb.2:
+ S_ENDPGM 0
+
+ bb.3:
+ S_ENDPGM 0
+...
>From 5790cf87efd73f8ea21b65ab34101af0632e5b7f Mon Sep 17 00:00:00 2001
From: Dark Steve <Prasoon.Mishra at amd.com>
Date: Mon, 16 Feb 2026 06:23:04 +0000
Subject: [PATCH 6/7] early return for backedges.
---
llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
index ad1ef6dbfd52c..d426cb39492b4 100644
--- a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
@@ -130,14 +130,16 @@ void SIPreEmitPeephole::updateMLIBeforeRemovingEdge(
BackEdgeCount++;
}
- if (BackEdgeCount <= 1) {
- MachineLoop *ParentLoop = Loop->getParentLoop();
+ if (BackEdgeCount > 1)
+ return;
- // Re-map blocks directly owned by this loop to the parent.
- for (MachineBasicBlock *BB : Loop->blocks()) {
- if (MLI->getLoopFor(BB) == Loop)
- MLI->changeLoopFor(BB, ParentLoop);
- }
+ MachineLoop *ParentLoop = Loop->getParentLoop();
+
+ // Re-map blocks directly owned by this loop to the parent.
+ for (MachineBasicBlock *BB : Loop->blocks()) {
+ if (MLI->getLoopFor(BB) == Loop)
+ MLI->changeLoopFor(BB, ParentLoop);
+ }
// Reparent all child loops.
while (!Loop->isInnermost()) {
@@ -154,7 +156,6 @@ void SIPreEmitPeephole::updateMLIBeforeRemovingEdge(
MLI->removeLoop(llvm::find(*MLI, Loop));
MLI->destroy(Loop);
- }
}
bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const {
>From a5f3d84ad75bb8cfb7abb80aae9287f5c4341ec5 Mon Sep 17 00:00:00 2001
From: Dark Steve <Prasoon.Mishra at amd.com>
Date: Mon, 16 Feb 2026 07:49:50 +0000
Subject: [PATCH 7/7] Apply clang-format on whole PR.
---
llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp | 24 ++++++++++----------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
index d426cb39492b4..fa5118aee69a4 100644
--- a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
@@ -141,21 +141,21 @@ void SIPreEmitPeephole::updateMLIBeforeRemovingEdge(
MLI->changeLoopFor(BB, ParentLoop);
}
- // Reparent all child loops.
- while (!Loop->isInnermost()) {
- MachineLoop *Child = Loop->removeChildLoop(std::prev(Loop->end()));
- if (ParentLoop)
- ParentLoop->addChildLoop(Child);
- else
- MLI->addTopLevelLoop(Child);
- }
-
+ // Reparent all child loops.
+ while (!Loop->isInnermost()) {
+ MachineLoop *Child = Loop->removeChildLoop(std::prev(Loop->end()));
if (ParentLoop)
- ParentLoop->removeChildLoop(Loop);
+ ParentLoop->addChildLoop(Child);
else
- MLI->removeLoop(llvm::find(*MLI, Loop));
+ MLI->addTopLevelLoop(Child);
+ }
+
+ if (ParentLoop)
+ ParentLoop->removeChildLoop(Loop);
+ else
+ MLI->removeLoop(llvm::find(*MLI, Loop));
- MLI->destroy(Loop);
+ MLI->destroy(Loop);
}
bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const {
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