[llvm] Optimize CTPOP lowering to match SelDAG (PR #181499)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 14 16:47:16 PST 2026
https://github.com/SiliconA-Z updated https://github.com/llvm/llvm-project/pull/181499
>From e1dcf1028549d57f726264b493da5b67cf8b1cc5 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 14 Feb 2026 13:14:15 -0500
Subject: [PATCH] [GlobalISel] Optimize CTPOP lowering to match SelDAG
Prevent multiplication when only having 16 bits.
---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 14 +++-
.../test/CodeGen/RISCV/GlobalISel/bitmanip.ll | 64 ++++++-------------
.../legalizer/legalize-ctls-rv32.mir | 15 ++---
.../legalizer/legalize-ctls-rv64.mir | 15 ++---
.../legalizer/legalize-ctlz-rv32.mir | 20 +++---
.../legalizer/legalize-ctlz-rv64.mir | 20 +++---
.../legalizer/legalize-ctpop-rv32.mir | 12 ++--
.../legalizer/legalize-ctpop-rv64.mir | 24 +++----
.../legalizer/legalize-cttz-rv32.mir | 24 +++----
.../legalizer/legalize-cttz-rv64.mir | 24 +++----
10 files changed, 103 insertions(+), 129 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 41b79ccb4e4d1..58e46f4f897e5 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -7799,7 +7799,19 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI) {
auto C_B8Mask4HiTo0 = B.buildConstant(Ty, B8Mask4HiTo0);
auto B8Count = B.buildAnd(Ty, B8CountDirty4Hi, C_B8Mask4HiTo0);
- assert(Size<=128 && "Scalar size is too large for CTPOP lower algorithm");
+ assert(Size <= 128 && "Scalar size is too large for CTPOP lower algorithm");
+
+ // Avoid the multiply when shift-add is cheaper.
+ if (Size == 16 && !Ty.isVector()) {
+ // v = (v + (v >> 8)) & 0xFF;
+ auto C_8 = B.buildConstant(Ty, 8);
+ auto HighSum = B.buildLShr(Ty, B8Count, C_8);
+ auto Res = B.buildAdd(Ty, B8Count, HighSum);
+ B.buildAnd(MI.getOperand(0).getReg(), Res, B.buildConstant(Ty, 0xFF));
+ MI.eraseFromParent();
+ return Legalized;
+ }
+
// 8 bits can hold CTPOP result of 128 bit int or smaller. Mul with this
// bitmask will set 8 msb in ResTmp to sum of all B8Counts in 8 bit blocks.
auto MulMask = B.buildConstant(Ty, APInt::getSplat(Size, APInt(8, 0x01)));
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
index cb12ef20b0994..c347241dff92f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
@@ -265,24 +265,17 @@ define i2 @test_ctpop_i2(i2 %a) {
define i11 @test_ctpop_i11(i11 %a) {
; RV32-LABEL: test_ctpop_i11:
; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32-NEXT: .cfi_offset ra, -4
-; RV32-NEXT: .cfi_offset s0, -8
; RV32-NEXT: andi a0, a0, 2047
; RV32-NEXT: lui a1, 5
-; RV32-NEXT: lui a2, 16
-; RV32-NEXT: srli a3, a0, 1
+; RV32-NEXT: srli a2, a0, 1
; RV32-NEXT: addi a1, a1, 1365
-; RV32-NEXT: and a1, a3, a1
-; RV32-NEXT: lui a3, 3
-; RV32-NEXT: addi s0, a2, -1
-; RV32-NEXT: addi a2, a3, 819
+; RV32-NEXT: and a1, a2, a1
+; RV32-NEXT: lui a2, 3
+; RV32-NEXT: addi a2, a2, 819
; RV32-NEXT: sub a0, a0, a1
-; RV32-NEXT: and a1, a0, s0
+; RV32-NEXT: slli a1, a0, 16
; RV32-NEXT: and a0, a0, a2
+; RV32-NEXT: srli a1, a1, 16
; RV32-NEXT: srli a1, a1, 2
; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: lui a2, 1
@@ -291,38 +284,24 @@ define i11 @test_ctpop_i11(i11 %a) {
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: addi a1, a2, -241
; RV32-NEXT: and a0, a0, a1
-; RV32-NEXT: li a1, 257
-; RV32-NEXT: call __mulsi3
-; RV32-NEXT: and a0, a0, s0
-; RV32-NEXT: srli a0, a0, 8
-; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32-NEXT: .cfi_restore ra
-; RV32-NEXT: .cfi_restore s0
-; RV32-NEXT: addi sp, sp, 16
-; RV32-NEXT: .cfi_def_cfa_offset 0
+; RV32-NEXT: srli a1, a0, 8
+; RV32-NEXT: add a0, a0, a1
+; RV32-NEXT: zext.b a0, a0
; RV32-NEXT: ret
;
; RV64-LABEL: test_ctpop_i11:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
-; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: .cfi_offset s0, -16
; RV64-NEXT: andi a0, a0, 2047
; RV64-NEXT: lui a1, 5
-; RV64-NEXT: lui a2, 16
-; RV64-NEXT: srli a3, a0, 1
+; RV64-NEXT: srli a2, a0, 1
; RV64-NEXT: addi a1, a1, 1365
-; RV64-NEXT: and a1, a3, a1
-; RV64-NEXT: lui a3, 3
-; RV64-NEXT: addi s0, a2, -1
-; RV64-NEXT: addi a2, a3, 819
+; RV64-NEXT: and a1, a2, a1
+; RV64-NEXT: lui a2, 3
+; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: sub a0, a0, a1
-; RV64-NEXT: and a1, a0, s0
+; RV64-NEXT: slli a1, a0, 48
; RV64-NEXT: and a0, a0, a2
+; RV64-NEXT: srli a1, a1, 48
; RV64-NEXT: srli a1, a1, 2
; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: lui a2, 1
@@ -331,16 +310,9 @@ define i11 @test_ctpop_i11(i11 %a) {
; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: addi a1, a2, -241
; RV64-NEXT: and a0, a0, a1
-; RV64-NEXT: li a1, 257
-; RV64-NEXT: call __muldi3
-; RV64-NEXT: and a0, a0, s0
-; RV64-NEXT: srli a0, a0, 8
-; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
-; RV64-NEXT: .cfi_restore ra
-; RV64-NEXT: .cfi_restore s0
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
+; RV64-NEXT: srli a1, a0, 8
+; RV64-NEXT: add a0, a0, a1
+; RV64-NEXT: zext.b a0, a0
; RV64-NEXT: ret
%1 = call i11 @llvm.ctpop.i11(i11 %a)
ret i11 %1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctls-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctls-rv32.mir
index 6f85a0a3c5a85..1b910a6c80d95 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctls-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctls-rv32.mir
@@ -151,16 +151,11 @@ body: |
; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD]]
; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855
; RV32I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C9]]
- ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
- ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; RV32I-NEXT: $x10 = COPY [[AND9]](s32)
- ; RV32I-NEXT: $x11 = COPY [[C10]](s32)
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C6]](s32)
- ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[LSHR7]]
+ ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C6]](s32)
+ ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND9]], [[LSHR7]]
+ ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; RV32I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C10]]
+ ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[AND10]]
; RV32I-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C1]]
; RV32I-NEXT: $x10 = COPY [[SUB2]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctls-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctls-rv64.mir
index 3ff9c44fd4ca3..46f1ceea5dc7c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctls-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctls-rv64.mir
@@ -153,17 +153,12 @@ body: |
; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR6]], [[ADD]]
; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 3855
; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C9]]
- ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 257
- ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; RV64I-NEXT: $x10 = COPY [[AND9]](s64)
- ; RV64I-NEXT: $x11 = COPY [[C10]](s64)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C3]]
- ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[AND10]], [[C6]](s64)
+ ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[AND9]], [[C6]](s64)
+ ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[AND9]], [[LSHR7]]
+ ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C10]]
; RV64I-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C11]], [[LSHR7]]
+ ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C11]], [[AND10]]
; RV64I-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[C1]]
; RV64I-NEXT: $x10 = COPY [[SUB2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv32.mir
index c2db4049580e1..eeae6ec21e13b 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv32.mir
@@ -112,12 +112,12 @@ body: |
; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD]]
; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855
; RV32I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]]
- ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
- ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND9]], [[C8]]
- ; RV32I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C1]]
- ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C4]](s32)
+ ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C4]](s32)
+ ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND9]], [[LSHR7]]
+ ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; RV32I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C8]]
; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C9]], [[LSHR7]]
+ ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C9]], [[AND10]]
; RV32I-NEXT: $x10 = COPY [[SUB1]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
@@ -410,12 +410,12 @@ body: |
; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD]]
; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855
; RV32I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]]
- ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
- ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND9]], [[C8]]
- ; RV32I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C1]]
- ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C4]](s32)
+ ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C4]](s32)
+ ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND9]], [[LSHR7]]
+ ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; RV32I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C8]]
; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C9]], [[LSHR7]]
+ ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C9]], [[AND10]]
; RV32I-NEXT: $x10 = COPY [[SUB1]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
index 62d731351ffd6..e75079d97d3a2 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
@@ -112,12 +112,12 @@ body: |
; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR6]], [[ADD]]
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3855
; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C7]]
- ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 257
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND9]], [[C8]]
- ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C1]]
- ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[AND10]], [[C4]](s64)
+ ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[AND9]], [[C4]](s64)
+ ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[AND9]], [[LSHR7]]
+ ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C8]]
; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C9]], [[LSHR7]]
+ ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C9]], [[AND10]]
; RV64I-NEXT: $x10 = COPY [[SUB1]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
@@ -387,12 +387,12 @@ body: |
; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR6]], [[ADD]]
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3855
; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C7]]
- ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 257
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND9]], [[C8]]
- ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C1]]
- ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[AND10]], [[C4]](s64)
+ ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[AND9]], [[C4]](s64)
+ ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[AND9]], [[LSHR7]]
+ ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C8]]
; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C9]], [[LSHR7]]
+ ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C9]], [[AND10]]
; RV64I-NEXT: $x10 = COPY [[SUB1]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv32.mir
index 7fdcd79d811aa..aa26191f44fc6 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv32.mir
@@ -86,12 +86,12 @@ body: |
; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]]
; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855
; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C6]]
- ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
- ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND5]], [[C7]]
- ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C1]]
- ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C8]](s32)
- ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)
+ ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C7]](s32)
+ ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[LSHR3]]
+ ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C8]]
+ ; RV32I-NEXT: $x10 = COPY [[AND6]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
; RV32ZBB-LABEL: name: ctpop_i16
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
index aae48cf7df6d0..ad6d6352cccd0 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
@@ -86,12 +86,12 @@ body: |
; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD]]
; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 3855
; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C6]]
- ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 257
- ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND5]], [[C7]]
- ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C1]]
- ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[C8]](s64)
- ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64)
+ ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[C7]](s64)
+ ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[AND5]], [[LSHR3]]
+ ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C8]]
+ ; RV64I-NEXT: $x10 = COPY [[AND6]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: ctpop_i16
@@ -302,12 +302,12 @@ body: |
; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD]]
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3855
; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C7]]
- ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 257
- ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND5]], [[C8]]
- ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C4]]
- ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[C9]](s64)
- ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64)
+ ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[C8]](s64)
+ ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[AND5]], [[LSHR3]]
+ ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C9]]
+ ; RV64I-NEXT: $x10 = COPY [[AND6]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: ctpop_i11
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv32.mir
index 6b2475be8a007..a4a06854fa18d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv32.mir
@@ -94,12 +94,12 @@ body: |
; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]]
; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855
; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]]
- ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
- ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND6]], [[C8]]
- ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C2]]
- ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[C9]](s32)
- ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)
+ ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C8]](s32)
+ ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[AND6]], [[LSHR3]]
+ ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C9]]
+ ; RV32I-NEXT: $x10 = COPY [[AND7]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
; RV32ZBB-LABEL: name: cttz_i16
@@ -344,12 +344,12 @@ body: |
; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]]
; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855
; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]]
- ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
- ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND6]], [[C8]]
- ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C2]]
- ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[C9]](s32)
- ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)
+ ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C8]](s32)
+ ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[AND6]], [[LSHR3]]
+ ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C9]]
+ ; RV32I-NEXT: $x10 = COPY [[AND7]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
; RV32ZBB-LABEL: name: cttz_zero_undef_i16
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
index 87155bb8b743e..82220a27d015d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
@@ -93,12 +93,12 @@ body: |
; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]]
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3855
; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C7]]
- ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 257
- ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND6]], [[C8]]
- ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C2]]
- ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[C9]](s64)
- ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64)
+ ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[C8]](s64)
+ ; RV64I-NEXT: [[ADD3:%[0-9]+]]:_(s64) = G_ADD [[AND6]], [[LSHR3]]
+ ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ADD3]], [[C9]]
+ ; RV64I-NEXT: $x10 = COPY [[AND7]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: cttz_i16
@@ -317,12 +317,12 @@ body: |
; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]]
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3855
; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C7]]
- ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 257
- ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND6]], [[C8]]
- ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C2]]
- ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[C9]](s64)
- ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64)
+ ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[C8]](s64)
+ ; RV64I-NEXT: [[ADD3:%[0-9]+]]:_(s64) = G_ADD [[AND6]], [[LSHR3]]
+ ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ADD3]], [[C9]]
+ ; RV64I-NEXT: $x10 = COPY [[AND7]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: cttz_zero_undef_i16
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