[llvm] [GlobalISel] port rewrite from SelectionDAG to GlobalISel (PR #181486)

[Osman Yasar via llvm-commits]

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@@ -413,3 +413,27 @@ body:             |
     $x0 = COPY %add
     RET_ReallyLR implicit $x0
 
+...
+---
+name:   APlusBPlusCMinusB
+body:             |
+  bb.0:
+    liveins: $w0, $w1
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osmanyasar05 wrote:

livein registers should be the ones that you use in lines 431-433. x type registers are 64-bit regs, and w type are 32-bit regs.

https://github.com/llvm/llvm-project/pull/181486