[llvm] 6e23353 - [DAGCombiner] Fix crash caused by illegal InterVT in ForwardStoreValueToDirectLoad (#181175)
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Sat Feb 14 05:05:35 PST 2026
Author: 陈子昂
Date: 2026-02-14T21:05:31+08:00
New Revision: 6e23353c396098bf5cedf26091179f9d8dacb2e9
URL: https://github.com/llvm/llvm-project/commit/6e23353c396098bf5cedf26091179f9d8dacb2e9
DIFF: https://github.com/llvm/llvm-project/commit/6e23353c396098bf5cedf26091179f9d8dacb2e9.diff
LOG: [DAGCombiner] Fix crash caused by illegal InterVT in ForwardStoreValueToDirectLoad (#181175)
This patch fixes an assertion failure in ForwardStoreValueToDirectLoad
during DAGCombine.
The crash occurs when `STLF (Store-to-Load Forwarding)` creates an
illegal intermediate bitcast type (e.g., `v128i1` when bridging a
128-bit store to a `<32 x i1>` load on X86). Since `v128i1` is not a
legal mask type for the backend, it violates the expectations of the
LegalizeDAG pass.
The fix adds a `TLI.isTypeLegal(InterVT)` check to ensure that the
intermediate type used for the transformation is supported by the
target.
Fixes #181130
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/X86/dag-stlf-mismatch.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 19bcdeeefb143..e513a16ee0e27 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -20831,7 +20831,8 @@ SDValue DAGCombiner::ForwardStoreValueToDirectLoad(LoadSDNode *LD) {
EVT InterVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
StMemSize.divideCoefficientBy(EltSize));
- if (!TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, LDMemType))
+ if (!TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, LDMemType) ||
+ !TLI.isTypeLegal(InterVT))
break;
// In case of big-endian the offset is normalized to zero, denoting
diff --git a/llvm/test/CodeGen/X86/dag-stlf-mismatch.ll b/llvm/test/CodeGen/X86/dag-stlf-mismatch.ll
index a1ee713b32032..309df51e303d8 100644
--- a/llvm/test/CodeGen/X86/dag-stlf-mismatch.ll
+++ b/llvm/test/CodeGen/X86/dag-stlf-mismatch.ll
@@ -1,15 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-pc-windows-gnu -mcpu=x86-64-v4 | FileCheck %s --check-prefix=AVX512
%struct.Data = type { float }
define float @test_stlf_integer(ptr %p, float %v) {
-; CHECK-LABEL: test_stlf_integer:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movl $0, (%rdi)
-; CHECK-NEXT: xorps %xmm1, %xmm1
-; CHECK-NEXT: mulss %xmm1, %xmm0
-; CHECK-NEXT: retq
+; X64-LABEL: test_stlf_integer:
+; X64: # %bb.0:
+; X64-NEXT: movl $0, (%rdi)
+; X64-NEXT: xorps %xmm1, %xmm1
+; X64-NEXT: mulss %xmm1, %xmm0
+; X64-NEXT: retq
+;
+; AVX512-LABEL: test_stlf_integer:
+; AVX512: # %bb.0:
+; AVX512-NEXT: movl $0, (%rcx)
+; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vmulss %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: retq
store i32 0, ptr %p, align 4
%f = load float, ptr %p, align 4
%r = fmul float %f, %v
@@ -17,12 +25,19 @@ define float @test_stlf_integer(ptr %p, float %v) {
}
define float @test_stlf_vector(ptr %p, float %v) {
-; CHECK-LABEL: test_stlf_vector:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorps %xmm1, %xmm1
-; CHECK-NEXT: movups %xmm1, (%rdi)
-; CHECK-NEXT: mulss (%rdi), %xmm0
-; CHECK-NEXT: retq
+; X64-LABEL: test_stlf_vector:
+; X64: # %bb.0:
+; X64-NEXT: xorps %xmm1, %xmm1
+; X64-NEXT: movups %xmm1, (%rdi)
+; X64-NEXT: mulss (%rdi), %xmm0
+; X64-NEXT: retq
+;
+; AVX512-LABEL: test_stlf_vector:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vmovups %xmm0, (%rcx)
+; AVX512-NEXT: vmulss (%rcx), %xmm1, %xmm0
+; AVX512-NEXT: retq
store <4 x float> zeroinitializer, ptr %p, align 4
%f = load float, ptr %p, align 4
%r = fmul float %f, %v
@@ -30,12 +45,19 @@ define float @test_stlf_vector(ptr %p, float %v) {
}
define float @test_stlf_bitcast(ptr %p, float %v) {
-; CHECK-LABEL: test_stlf_bitcast:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorps %xmm1, %xmm1
-; CHECK-NEXT: movups %xmm1, (%rdi)
-; CHECK-NEXT: mulss (%rdi), %xmm0
-; CHECK-NEXT: retq
+; X64-LABEL: test_stlf_bitcast:
+; X64: # %bb.0:
+; X64-NEXT: xorps %xmm1, %xmm1
+; X64-NEXT: movups %xmm1, (%rdi)
+; X64-NEXT: mulss (%rdi), %xmm0
+; X64-NEXT: retq
+;
+; AVX512-LABEL: test_stlf_bitcast:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vmovups %xmm0, (%rcx)
+; AVX512-NEXT: vmulss (%rcx), %xmm1, %xmm0
+; AVX512-NEXT: retq
store <2 x i64> zeroinitializer, ptr %p, align 4
%f = load float, ptr %p, align 4
%r = fmul float %f, %v
@@ -44,28 +66,65 @@ define float @test_stlf_bitcast(ptr %p, float %v) {
declare void @ext_func(ptr byval(%struct.Data) align 4 %p)
define void @test_stlf_late_byval(ptr %ptr) nounwind {
-; CHECK-LABEL: test_stlf_late_byval:
-; CHECK: # %bb.0:
-; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: movl $0, (%rdi)
-; CHECK-NEXT: movl $0, (%rsp)
-; CHECK-NEXT: callq ext_func at PLT
-; CHECK-NEXT: popq %rax
-; CHECK-NEXT: retq
+; X64-LABEL: test_stlf_late_byval:
+; X64: # %bb.0:
+; X64-NEXT: pushq %rax
+; X64-NEXT: movl $0, (%rdi)
+; X64-NEXT: movl $0, (%rsp)
+; X64-NEXT: callq ext_func at PLT
+; X64-NEXT: popq %rax
+; X64-NEXT: retq
+;
+; AVX512-LABEL: test_stlf_late_byval:
+; AVX512: # %bb.0:
+; AVX512-NEXT: subq $40, %rsp
+; AVX512-NEXT: movl $0, (%rcx)
+; AVX512-NEXT: movl $0, {{[0-9]+}}(%rsp)
+; AVX512-NEXT: leaq {{[0-9]+}}(%rsp), %rcx
+; AVX512-NEXT: callq ext_func
+; AVX512-NEXT: addq $40, %rsp
+; AVX512-NEXT: retq
store i32 0, ptr %ptr, align 4
call void @ext_func(ptr byval(%struct.Data) align 4 %ptr)
ret void
}
define float @test_stlf_variable(ptr %p, i32 %val, float %v) {
-; CHECK-LABEL: test_stlf_variable:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movd %esi, %xmm1
-; CHECK-NEXT: movl %esi, (%rdi)
-; CHECK-NEXT: mulss %xmm1, %xmm0
-; CHECK-NEXT: retq
+; X64-LABEL: test_stlf_variable:
+; X64: # %bb.0:
+; X64-NEXT: movd %esi, %xmm1
+; X64-NEXT: movl %esi, (%rdi)
+; X64-NEXT: mulss %xmm1, %xmm0
+; X64-NEXT: retq
+;
+; AVX512-LABEL: test_stlf_variable:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vmovd %edx, %xmm0
+; AVX512-NEXT: movl %edx, (%rcx)
+; AVX512-NEXT: vmulss %xmm2, %xmm0, %xmm0
+; AVX512-NEXT: retq
store i32 %val, ptr %p, align 4
%f = load float, ptr %p, align 4
%r = fmul float %f, %v
ret float %r
}
+
+define <32 x i1> @v32i1_bitcast_crash(<4 x i8> %arg) nounwind {
+; X64-LABEL: v32i1_bitcast_crash:
+; X64: # %bb.0:
+; X64-NEXT: movq %rdi, %rax
+; X64-NEXT: movss %xmm0, (%rdi)
+; X64-NEXT: retq
+;
+; AVX512-LABEL: v32i1_bitcast_crash:
+; AVX512: # %bb.0:
+; AVX512-NEXT: subq $24, %rsp
+; AVX512-NEXT: vmovaps (%rcx), %xmm0
+; AVX512-NEXT: vmovaps %xmm0, (%rsp)
+; AVX512-NEXT: kmovd (%rsp), %k0
+; AVX512-NEXT: vpmovm2b %k0, %ymm0
+; AVX512-NEXT: addq $24, %rsp
+; AVX512-NEXT: retq
+ %res = bitcast <4 x i8> %arg to <32 x i1>
+ ret <32 x i1> %res
+}
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