[llvm] [DAGCombiner] Fix crash caused by illegal InterVT in ForwardStoreValueToDirectLoad (PR #181175)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 14 04:13:05 PST 2026
https://github.com/Michael-Chen-NJU updated https://github.com/llvm/llvm-project/pull/181175
>From 282956a57cbd16a7821d8c4bc6f81525a5d55aad Mon Sep 17 00:00:00 2001
From: Michael-Chen-NJU <2802328816 at qq.com>
Date: Fri, 13 Feb 2026 00:26:32 +0800
Subject: [PATCH 1/3] [DAGCombine] Fix crash caused by illegal InterVT in
ForwardStoreValueToDirectLoad
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 ++-
.../CodeGen/X86/stlf-v32i1-bitcast-crash.ll | 21 +++++++++++++++++++
2 files changed, 23 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/X86/stlf-v32i1-bitcast-crash.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 19bcdeeefb143..e513a16ee0e27 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -20831,7 +20831,8 @@ SDValue DAGCombiner::ForwardStoreValueToDirectLoad(LoadSDNode *LD) {
EVT InterVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
StMemSize.divideCoefficientBy(EltSize));
- if (!TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, LDMemType))
+ if (!TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, LDMemType) ||
+ !TLI.isTypeLegal(InterVT))
break;
// In case of big-endian the offset is normalized to zero, denoting
diff --git a/llvm/test/CodeGen/X86/stlf-v32i1-bitcast-crash.ll b/llvm/test/CodeGen/X86/stlf-v32i1-bitcast-crash.ll
new file mode 100644
index 0000000000000..2abdc547dd479
--- /dev/null
+++ b/llvm/test/CodeGen/X86/stlf-v32i1-bitcast-crash.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-pc-windows-gnu -mcpu=tigerlake | FileCheck %s
+
+define <32 x i1> @v32i1_bitcast_crash(<4 x i8> %0) {
+; CHECK-LABEL: v32i1_bitcast_crash:
+; CHECK: # %bb.0:
+; CHECK-NEXT: subq $24, %rsp
+; CHECK-NEXT: .seh_stackalloc 24
+; CHECK-NEXT: .seh_endprologue
+; CHECK-NEXT: vmovaps (%rcx), %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp)
+; CHECK-NEXT: kmovd (%rsp), %k0
+; CHECK-NEXT: vpmovm2b %k0, %ymm0
+; CHECK-NEXT: .seh_startepilogue
+; CHECK-NEXT: addq $24, %rsp
+; CHECK-NEXT: .seh_endepilogue
+; CHECK-NEXT: retq
+; CHECK-NEXT: .seh_endproc
+ %2 = bitcast <4 x i8> %0 to <32 x i1>
+ ret <32 x i1> %2
+}
>From 78349b3a63489d38c61e4017817c5ce583645049 Mon Sep 17 00:00:00 2001
From: Michael-Chen-NJU <2802328816 at qq.com>
Date: Wed, 11 Feb 2026 01:37:11 +0800
Subject: [PATCH 2/3] [DAGCombiner] Fix subvector extraction index for
big-endian STLF
---
llvm/test/CodeGen/X86/dag-stlf-mismatch.ll | 16 +++++++++++++-
.../CodeGen/X86/stlf-v32i1-bitcast-crash.ll | 21 -------------------
2 files changed, 15 insertions(+), 22 deletions(-)
delete mode 100644 llvm/test/CodeGen/X86/stlf-v32i1-bitcast-crash.ll
diff --git a/llvm/test/CodeGen/X86/dag-stlf-mismatch.ll b/llvm/test/CodeGen/X86/dag-stlf-mismatch.ll
index a1ee713b32032..5c46b7a8dbdc4 100644
--- a/llvm/test/CodeGen/X86/dag-stlf-mismatch.ll
+++ b/llvm/test/CodeGen/X86/dag-stlf-mismatch.ll
@@ -1,5 +1,5 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-pc-windows-gnu -mcpu=tigerlake | FileCheck %s --check-prefix=TIGER
%struct.Data = type { float }
@@ -69,3 +69,17 @@ define float @test_stlf_variable(ptr %p, i32 %val, float %v) {
%r = fmul float %f, %v
ret float %r
}
+
+define <32 x i1> @v32i1_bitcast_crash(<4 x i8> %arg) nounwind {
+; TIGER-LABEL: v32i1_bitcast_crash:
+; TIGER: # %bb.0:
+; TIGER-NEXT: subq $24, %rsp
+; TIGER-NEXT: vmovaps (%rcx), %xmm0
+; TIGER-NEXT: vmovaps %xmm0, (%rsp)
+; TIGER-NEXT: kmovd (%rsp), %k0
+; TIGER-NEXT: vpmovm2b %k0, %ymm0
+; TIGER-NEXT: addq $24, %rsp
+; TIGER-NEXT: retq
+ %res = bitcast <4 x i8> %arg to <32 x i1>
+ ret <32 x i1> %res
+}
diff --git a/llvm/test/CodeGen/X86/stlf-v32i1-bitcast-crash.ll b/llvm/test/CodeGen/X86/stlf-v32i1-bitcast-crash.ll
deleted file mode 100644
index 2abdc547dd479..0000000000000
--- a/llvm/test/CodeGen/X86/stlf-v32i1-bitcast-crash.ll
+++ /dev/null
@@ -1,21 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc < %s -mtriple=x86_64-pc-windows-gnu -mcpu=tigerlake | FileCheck %s
-
-define <32 x i1> @v32i1_bitcast_crash(<4 x i8> %0) {
-; CHECK-LABEL: v32i1_bitcast_crash:
-; CHECK: # %bb.0:
-; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: .seh_stackalloc 24
-; CHECK-NEXT: .seh_endprologue
-; CHECK-NEXT: vmovaps (%rcx), %xmm0
-; CHECK-NEXT: vmovaps %xmm0, (%rsp)
-; CHECK-NEXT: kmovd (%rsp), %k0
-; CHECK-NEXT: vpmovm2b %k0, %ymm0
-; CHECK-NEXT: .seh_startepilogue
-; CHECK-NEXT: addq $24, %rsp
-; CHECK-NEXT: .seh_endepilogue
-; CHECK-NEXT: retq
-; CHECK-NEXT: .seh_endproc
- %2 = bitcast <4 x i8> %0 to <32 x i1>
- ret <32 x i1> %2
-}
>From a51efeb8af78bdbf831c571e7bafbe9fafbd16e8 Mon Sep 17 00:00:00 2001
From: Michael-Chen-NJU <2802328816 at qq.com>
Date: Sat, 14 Feb 2026 20:12:39 +0800
Subject: [PATCH 3/3] update test
---
llvm/test/CodeGen/X86/dag-stlf-mismatch.ll | 131 ++++++++++++++-------
1 file changed, 88 insertions(+), 43 deletions(-)
diff --git a/llvm/test/CodeGen/X86/dag-stlf-mismatch.ll b/llvm/test/CodeGen/X86/dag-stlf-mismatch.ll
index 5c46b7a8dbdc4..309df51e303d8 100644
--- a/llvm/test/CodeGen/X86/dag-stlf-mismatch.ll
+++ b/llvm/test/CodeGen/X86/dag-stlf-mismatch.ll
@@ -1,15 +1,23 @@
-; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-pc-windows-gnu -mcpu=tigerlake | FileCheck %s --check-prefix=TIGER
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-pc-windows-gnu -mcpu=x86-64-v4 | FileCheck %s --check-prefix=AVX512
%struct.Data = type { float }
define float @test_stlf_integer(ptr %p, float %v) {
-; CHECK-LABEL: test_stlf_integer:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movl $0, (%rdi)
-; CHECK-NEXT: xorps %xmm1, %xmm1
-; CHECK-NEXT: mulss %xmm1, %xmm0
-; CHECK-NEXT: retq
+; X64-LABEL: test_stlf_integer:
+; X64: # %bb.0:
+; X64-NEXT: movl $0, (%rdi)
+; X64-NEXT: xorps %xmm1, %xmm1
+; X64-NEXT: mulss %xmm1, %xmm0
+; X64-NEXT: retq
+;
+; AVX512-LABEL: test_stlf_integer:
+; AVX512: # %bb.0:
+; AVX512-NEXT: movl $0, (%rcx)
+; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vmulss %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: retq
store i32 0, ptr %p, align 4
%f = load float, ptr %p, align 4
%r = fmul float %f, %v
@@ -17,12 +25,19 @@ define float @test_stlf_integer(ptr %p, float %v) {
}
define float @test_stlf_vector(ptr %p, float %v) {
-; CHECK-LABEL: test_stlf_vector:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorps %xmm1, %xmm1
-; CHECK-NEXT: movups %xmm1, (%rdi)
-; CHECK-NEXT: mulss (%rdi), %xmm0
-; CHECK-NEXT: retq
+; X64-LABEL: test_stlf_vector:
+; X64: # %bb.0:
+; X64-NEXT: xorps %xmm1, %xmm1
+; X64-NEXT: movups %xmm1, (%rdi)
+; X64-NEXT: mulss (%rdi), %xmm0
+; X64-NEXT: retq
+;
+; AVX512-LABEL: test_stlf_vector:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vmovups %xmm0, (%rcx)
+; AVX512-NEXT: vmulss (%rcx), %xmm1, %xmm0
+; AVX512-NEXT: retq
store <4 x float> zeroinitializer, ptr %p, align 4
%f = load float, ptr %p, align 4
%r = fmul float %f, %v
@@ -30,12 +45,19 @@ define float @test_stlf_vector(ptr %p, float %v) {
}
define float @test_stlf_bitcast(ptr %p, float %v) {
-; CHECK-LABEL: test_stlf_bitcast:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorps %xmm1, %xmm1
-; CHECK-NEXT: movups %xmm1, (%rdi)
-; CHECK-NEXT: mulss (%rdi), %xmm0
-; CHECK-NEXT: retq
+; X64-LABEL: test_stlf_bitcast:
+; X64: # %bb.0:
+; X64-NEXT: xorps %xmm1, %xmm1
+; X64-NEXT: movups %xmm1, (%rdi)
+; X64-NEXT: mulss (%rdi), %xmm0
+; X64-NEXT: retq
+;
+; AVX512-LABEL: test_stlf_bitcast:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vmovups %xmm0, (%rcx)
+; AVX512-NEXT: vmulss (%rcx), %xmm1, %xmm0
+; AVX512-NEXT: retq
store <2 x i64> zeroinitializer, ptr %p, align 4
%f = load float, ptr %p, align 4
%r = fmul float %f, %v
@@ -44,26 +66,43 @@ define float @test_stlf_bitcast(ptr %p, float %v) {
declare void @ext_func(ptr byval(%struct.Data) align 4 %p)
define void @test_stlf_late_byval(ptr %ptr) nounwind {
-; CHECK-LABEL: test_stlf_late_byval:
-; CHECK: # %bb.0:
-; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: movl $0, (%rdi)
-; CHECK-NEXT: movl $0, (%rsp)
-; CHECK-NEXT: callq ext_func at PLT
-; CHECK-NEXT: popq %rax
-; CHECK-NEXT: retq
+; X64-LABEL: test_stlf_late_byval:
+; X64: # %bb.0:
+; X64-NEXT: pushq %rax
+; X64-NEXT: movl $0, (%rdi)
+; X64-NEXT: movl $0, (%rsp)
+; X64-NEXT: callq ext_func at PLT
+; X64-NEXT: popq %rax
+; X64-NEXT: retq
+;
+; AVX512-LABEL: test_stlf_late_byval:
+; AVX512: # %bb.0:
+; AVX512-NEXT: subq $40, %rsp
+; AVX512-NEXT: movl $0, (%rcx)
+; AVX512-NEXT: movl $0, {{[0-9]+}}(%rsp)
+; AVX512-NEXT: leaq {{[0-9]+}}(%rsp), %rcx
+; AVX512-NEXT: callq ext_func
+; AVX512-NEXT: addq $40, %rsp
+; AVX512-NEXT: retq
store i32 0, ptr %ptr, align 4
call void @ext_func(ptr byval(%struct.Data) align 4 %ptr)
ret void
}
define float @test_stlf_variable(ptr %p, i32 %val, float %v) {
-; CHECK-LABEL: test_stlf_variable:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movd %esi, %xmm1
-; CHECK-NEXT: movl %esi, (%rdi)
-; CHECK-NEXT: mulss %xmm1, %xmm0
-; CHECK-NEXT: retq
+; X64-LABEL: test_stlf_variable:
+; X64: # %bb.0:
+; X64-NEXT: movd %esi, %xmm1
+; X64-NEXT: movl %esi, (%rdi)
+; X64-NEXT: mulss %xmm1, %xmm0
+; X64-NEXT: retq
+;
+; AVX512-LABEL: test_stlf_variable:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vmovd %edx, %xmm0
+; AVX512-NEXT: movl %edx, (%rcx)
+; AVX512-NEXT: vmulss %xmm2, %xmm0, %xmm0
+; AVX512-NEXT: retq
store i32 %val, ptr %p, align 4
%f = load float, ptr %p, align 4
%r = fmul float %f, %v
@@ -71,15 +110,21 @@ define float @test_stlf_variable(ptr %p, i32 %val, float %v) {
}
define <32 x i1> @v32i1_bitcast_crash(<4 x i8> %arg) nounwind {
-; TIGER-LABEL: v32i1_bitcast_crash:
-; TIGER: # %bb.0:
-; TIGER-NEXT: subq $24, %rsp
-; TIGER-NEXT: vmovaps (%rcx), %xmm0
-; TIGER-NEXT: vmovaps %xmm0, (%rsp)
-; TIGER-NEXT: kmovd (%rsp), %k0
-; TIGER-NEXT: vpmovm2b %k0, %ymm0
-; TIGER-NEXT: addq $24, %rsp
-; TIGER-NEXT: retq
+; X64-LABEL: v32i1_bitcast_crash:
+; X64: # %bb.0:
+; X64-NEXT: movq %rdi, %rax
+; X64-NEXT: movss %xmm0, (%rdi)
+; X64-NEXT: retq
+;
+; AVX512-LABEL: v32i1_bitcast_crash:
+; AVX512: # %bb.0:
+; AVX512-NEXT: subq $24, %rsp
+; AVX512-NEXT: vmovaps (%rcx), %xmm0
+; AVX512-NEXT: vmovaps %xmm0, (%rsp)
+; AVX512-NEXT: kmovd (%rsp), %k0
+; AVX512-NEXT: vpmovm2b %k0, %ymm0
+; AVX512-NEXT: addq $24, %rsp
+; AVX512-NEXT: retq
%res = bitcast <4 x i8> %arg to <32 x i1>
ret <32 x i1> %res
}
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