[llvm] [NFC][CodeGen] Simplify sub-register verification in MIR (PR #181423)

[Rahul Joshi via llvm-commits]

https://github.com/jurahul created https://github.com/llvm/llvm-project/pull/181423

None

>From 9acac7afb354a3beb33210dc47eaffc6831774ce Mon Sep 17 00:00:00 2001
From: Rahul Joshi <rjoshi at nvidia.com>
Date: Fri, 13 Feb 2026 13:26:57 -0800
Subject: [PATCH] [NFC][CodeGen] Simplify sub-register verification in MIR

---
 llvm/lib/CodeGen/MachineVerifier.cpp          | 43 ++++++-------------
 ...ported-subreg-index-aligned-vgpr-check.mir | 11 +++++
 2 files changed, 24 insertions(+), 30 deletions(-)

diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 919d451e25e54..3c7a5ded6ef2d 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -2800,45 +2800,28 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
 
         break;
       }
+      const TargetRegisterClass *EffectiveRC = RC;
       if (SubIdx) {
-        const TargetRegisterClass *SRC =
-          TRI->getSubClassWithSubReg(RC, SubIdx);
-        if (!SRC) {
+        // If a virtual register is used with a SubRegIndex, compute the
+        // effective register class after applying that SubRegIndex to the
+        // virtual register's class.
+        EffectiveRC = TRI->getSubRegisterClass(RC, SubIdx);
+
+        if (!EffectiveRC) {
           report("Invalid subregister index for virtual register", MO, MONum);
           OS << "Register class " << TRI->getRegClassName(RC)
              << " does not support subreg index "
              << TRI->getSubRegIndexName(SubIdx) << '\n';
           return;
         }
-        if (RC != SRC) {
-          report("Invalid register class for subregister index", MO, MONum);
-          OS << "Register class " << TRI->getRegClassName(RC)
-             << " does not fully support subreg index "
-             << TRI->getSubRegIndexName(SubIdx) << '\n';
-          return;
-        }
       }
       if (MONum < MCID.getNumOperands()) {
-        if (const TargetRegisterClass *DRC = TII->getRegClass(MCID, MONum)) {
-          if (SubIdx) {
-            const TargetRegisterClass *SuperRC =
-                TRI->getLargestLegalSuperClass(RC, *MF);
-            if (!SuperRC) {
-              report("No largest legal super class exists.", MO, MONum);
-              return;
-            }
-            DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
-            if (!DRC) {
-              report("No matching super-reg register class.", MO, MONum);
-              return;
-            }
-          }
-          if (!RC->hasSuperClassEq(DRC)) {
-            report("Illegal virtual register for instruction", MO, MONum);
-            OS << "Expected a " << TRI->getRegClassName(DRC)
-               << " register, but got a " << TRI->getRegClassName(RC)
-               << " register\n";
-          }
+        if (const TargetRegisterClass *DRC = TII->getRegClass(MCID, MONum);
+            DRC && !EffectiveRC->hasSuperClassEq(DRC)) {
+          report("Illegal virtual register for instruction", MO, MONum);
+          OS << "Expected a " << TRI->getRegClassName(DRC)
+             << " register, but got a " << TRI->getRegClassName(EffectiveRC)
+             << " register\n";
         }
       }
     }
diff --git a/llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir b/llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
index be1311cb6b217..7dfa0c03426ff 100644
--- a/llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
+++ b/llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
@@ -36,6 +36,17 @@ body:             |
     ; CHECK-NEXT: Register class VReg_512 does not support subreg index sub16_sub17_sub18_sub19
     S_NOP 0, implicit-def %2:vreg_512
     GLOBAL_STORE_DWORDX4_SADDR %0, %2.sub16_sub17_sub18_sub19, undef $sgpr8_sgpr9, 80, 0, implicit $exec :: (store (s128), addrspace 1)
+
+    ; Test valid subregister index, but invalid effective register class.
+    ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+    ; CHECK-NEXT: - function:    uses_invalid_subregister_for_regclass
+    ; CHECK-NEXT: - basic block: %bb.0
+    ; CHECK-NEXT: - instruction: GLOBAL_STORE_DWORDX4_SADDR %0:vgpr_32, %2.sub0:vreg_512, undef $sgpr8_sgpr9, 80, 0, implicit $exec :: (store (s128), addrspace 1)
+    ; CHECK-NEXT: - operand 1:   %2.sub0:vreg_512
+    ; CHECK-NEXT: Expected a AV_128_Align2 register, but got a VGPR_32 register
+    %3:sreg_32 = COPY %0
+    GLOBAL_STORE_DWORDX4_SADDR %0, %2.sub0, undef $sgpr8_sgpr9, 80, 0, implicit $exec :: (store (s128), addrspace 1)
+
     S_ENDPGM 0
 
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