[llvm] [AMDGPU][NFC] Enable RegistersAreIntervals (PR #181398)

[Ryan Mitchell via llvm-commits]

https://github.com/RyanRio created https://github.com/llvm/llvm-project/pull/181398

Turn on the target option added in #175823. Just turning it on is NFC, I'm planning on revisiting #174888 after some more downstream work.

>From f8cdfa565cd5264a962514e76d4910c4e1d90aef Mon Sep 17 00:00:00 2001
From: Ryan Mitchell <Ryan.Mitchell at amd.com>
Date: Fri, 13 Feb 2026 10:36:43 -0800
Subject: [PATCH] [AMDGPU][NFC] Enable RegistersAreIntervals

---
 llvm/lib/Target/AMDGPU/AMDGPU.td | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 9d723c86031f2..50a0bfc5a7763 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -2181,6 +2181,7 @@ def AMDGPU : Target {
                                 VOP3_DPPAsmParserVariant];
   let AssemblyWriters = [AMDGPUAsmWriter];
   let AllowRegisterRenaming = 1;
+  let RegistersAreIntervals  = 1;
 }
 
 // Dummy Instruction itineraries for pseudo instructions