[llvm] [NFC] Pre-Commit test case for __builtin_ppc_test_data_class (PR #181181)
zhijian lin via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 13 06:44:21 PST 2026
https://github.com/diggerlin updated https://github.com/llvm/llvm-project/pull/181181
>From 3e7fa42906636b0857d11a68249a1e6ffde6350b Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Thu, 12 Feb 2026 11:45:12 -0500
Subject: [PATCH 1/5] add precommit test case for __builtin_ppc_test_data_class
---
.../CodeGen/PowerPC/ppc_test_data_class.ll | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
diff --git a/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll b/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
new file mode 100644
index 0000000000000..7e9e7bece3f1f
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
@@ -0,0 +1,77 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck --check-prefix=AIX-PWR9 %s
+; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -verify-machineinstrs -mcpu=pwr10 < %s | FileCheck --check-prefix=AIX-PWR10 %s
+; RUN: llc -mtriple=powerpc-ibm64-aix7.2.0.0 -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck --check-prefix=AIX-PWR9 %s
+; RUN: llc -mtriple=powerpc-ibm64-aix7.2.0.0 -verify-machineinstrs -mcpu=pwr10 < %s | FileCheck --check-prefix=AIX-PWR10 %s
+; RUN: llc -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck --check-prefix=LNXLE64-PWR9 %s
+; RUN: llc -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs -mcpu=pwr10 < %s | FileCheck --check-prefix=LNXLE64-PWR10 %s
+; RUN: llc -mtriple=powerpcle-unknown-unknown -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck --check-prefix=LNXLE-PWR9 %s
+; RUN: llc -mtriple=powerpcle-unknown-unknown -verify-machineinstrs -mcpu=pwr10 < %s | FileCheck --check-prefix=LNXLE-PWR10 %s
+define noundef zeroext i1 @_Z16ossIsValidDoubled(double noundef %in) local_unnamed_addr {
+; AIX-PWR9-LABEL: _Z16ossIsValidDoubled:
+; AIX-PWR9: # %bb.0: # %entry
+; AIX-PWR9-NEXT: xststdcdp 0, 1, 115
+; AIX-PWR9-NEXT: li 3, 0
+; AIX-PWR9-NEXT: li 4, 1
+; AIX-PWR9-NEXT: iseleq 3, 4, 3
+; AIX-PWR9-NEXT: cntlzw 3, 3
+; AIX-PWR9-NEXT: rlwinm 3, 3, 27, 31, 31
+; AIX-PWR9-NEXT: blr
+;
+; AIX-PWR10-LABEL: _Z16ossIsValidDoubled:
+; AIX-PWR10: # %bb.0: # %entry
+; AIX-PWR10-NEXT: xststdcdp 0, 1, 115
+; AIX-PWR10-NEXT: li 3, 0
+; AIX-PWR10-NEXT: li 4, 1
+; AIX-PWR10-NEXT: iseleq 3, 4, 3
+; AIX-PWR10-NEXT: cntlzw 3, 3
+; AIX-PWR10-NEXT: rlwinm 3, 3, 27, 31, 31
+; AIX-PWR10-NEXT: blr
+;
+; LNXLE64-PWR9-LABEL: _Z16ossIsValidDoubled:
+; LNXLE64-PWR9: # %bb.0: # %entry
+; LNXLE64-PWR9-NEXT: xststdcdp 0, 1, 115
+; LNXLE64-PWR9-NEXT: li 3, 0
+; LNXLE64-PWR9-NEXT: li 4, 1
+; LNXLE64-PWR9-NEXT: iseleq 3, 4, 3
+; LNXLE64-PWR9-NEXT: cntlzw 3, 3
+; LNXLE64-PWR9-NEXT: srwi 3, 3, 5
+; LNXLE64-PWR9-NEXT: blr
+;
+; LNXLE64-PWR10-LABEL: _Z16ossIsValidDoubled:
+; LNXLE64-PWR10: # %bb.0: # %entry
+; LNXLE64-PWR10-NEXT: xststdcdp 0, 1, 115
+; LNXLE64-PWR10-NEXT: li 3, 0
+; LNXLE64-PWR10-NEXT: li 4, 1
+; LNXLE64-PWR10-NEXT: iseleq 3, 4, 3
+; LNXLE64-PWR10-NEXT: cntlzw 3, 3
+; LNXLE64-PWR10-NEXT: rlwinm 3, 3, 27, 31, 31
+; LNXLE64-PWR10-NEXT: blr
+;
+; LNXLE-PWR9-LABEL: _Z16ossIsValidDoubled:
+; LNXLE-PWR9: # %bb.0: # %entry
+; LNXLE-PWR9-NEXT: xststdcdp 0, 1, 115
+; LNXLE-PWR9-NEXT: li 3, 0
+; LNXLE-PWR9-NEXT: li 4, 1
+; LNXLE-PWR9-NEXT: iseleq 3, 4, 3
+; LNXLE-PWR9-NEXT: cntlzw 3, 3
+; LNXLE-PWR9-NEXT: rlwinm 3, 3, 27, 31, 31
+; LNXLE-PWR9-NEXT: blr
+;
+; LNXLE-PWR10-LABEL: _Z16ossIsValidDoubled:
+; LNXLE-PWR10: # %bb.0: # %entry
+; LNXLE-PWR10-NEXT: xststdcdp 0, 1, 115
+; LNXLE-PWR10-NEXT: li 3, 0
+; LNXLE-PWR10-NEXT: li 4, 1
+; LNXLE-PWR10-NEXT: iseleq 3, 4, 3
+; LNXLE-PWR10-NEXT: cntlzw 3, 3
+; LNXLE-PWR10-NEXT: rlwinm 3, 3, 27, 31, 31
+; LNXLE-PWR10-NEXT: blr
+entry:
+ %test_data_class = tail call i32 @llvm.ppc.test.data.class.f64(double %in, i32 115)
+ %tobool.not = icmp eq i32 %test_data_class, 0
+ ret i1 %tobool.not
+}
+
+declare i32 @llvm.ppc.test.data.class.f64(double, i32 immarg)
+
>From 8f74c970278b8cef047d4cb1bc82403d2181c9bb Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Thu, 12 Feb 2026 11:54:27 -0500
Subject: [PATCH 2/5] add -ppc-asm-full-reg-names into testcase
---
.../CodeGen/PowerPC/ppc_test_data_class.ll | 88 +++++++++----------
1 file changed, 44 insertions(+), 44 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll b/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
index 7e9e7bece3f1f..6509baf7e3a48 100644
--- a/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
@@ -1,71 +1,71 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck --check-prefix=AIX-PWR9 %s
-; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -verify-machineinstrs -mcpu=pwr10 < %s | FileCheck --check-prefix=AIX-PWR10 %s
-; RUN: llc -mtriple=powerpc-ibm64-aix7.2.0.0 -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck --check-prefix=AIX-PWR9 %s
-; RUN: llc -mtriple=powerpc-ibm64-aix7.2.0.0 -verify-machineinstrs -mcpu=pwr10 < %s | FileCheck --check-prefix=AIX-PWR10 %s
-; RUN: llc -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck --check-prefix=LNXLE64-PWR9 %s
-; RUN: llc -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs -mcpu=pwr10 < %s | FileCheck --check-prefix=LNXLE64-PWR10 %s
-; RUN: llc -mtriple=powerpcle-unknown-unknown -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck --check-prefix=LNXLE-PWR9 %s
-; RUN: llc -mtriple=powerpcle-unknown-unknown -verify-machineinstrs -mcpu=pwr10 < %s | FileCheck --check-prefix=LNXLE-PWR10 %s
+; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=AIX-PWR9 %s
+; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=AIX-PWR10 %s
+; RUN: llc -mtriple=powerpc-ibm64-aix7.2.0.0 -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=AIX-PWR9 %s
+; RUN: llc -mtriple=powerpc-ibm64-aix7.2.0.0 -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=AIX-PWR10 %s
+; RUN: llc -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 -ppc-asm-full-reg-names< %s | FileCheck --check-prefix=LNXLE64-PWR9 %s
+; RUN: llc -mtriple=powerpc64le-unknown-unknown -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=LNXLE64-PWR10 %s
+; RUN: llc -mtriple=powerpcle-unknown-unknown -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=LNXLE-PWR9 %s
+; RUN: llc -mtriple=powerpcle-unknown-unknown -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=LNXLE-PWR10 %s
define noundef zeroext i1 @_Z16ossIsValidDoubled(double noundef %in) local_unnamed_addr {
; AIX-PWR9-LABEL: _Z16ossIsValidDoubled:
; AIX-PWR9: # %bb.0: # %entry
-; AIX-PWR9-NEXT: xststdcdp 0, 1, 115
-; AIX-PWR9-NEXT: li 3, 0
-; AIX-PWR9-NEXT: li 4, 1
-; AIX-PWR9-NEXT: iseleq 3, 4, 3
-; AIX-PWR9-NEXT: cntlzw 3, 3
-; AIX-PWR9-NEXT: rlwinm 3, 3, 27, 31, 31
+; AIX-PWR9-NEXT: xststdcdp cr0, f1, 115
+; AIX-PWR9-NEXT: li r3, 0
+; AIX-PWR9-NEXT: li r4, 1
+; AIX-PWR9-NEXT: iseleq r3, r4, r3
+; AIX-PWR9-NEXT: cntlzw r3, r3
+; AIX-PWR9-NEXT: rlwinm r3, r3, 27, 31, 31
; AIX-PWR9-NEXT: blr
;
; AIX-PWR10-LABEL: _Z16ossIsValidDoubled:
; AIX-PWR10: # %bb.0: # %entry
-; AIX-PWR10-NEXT: xststdcdp 0, 1, 115
-; AIX-PWR10-NEXT: li 3, 0
-; AIX-PWR10-NEXT: li 4, 1
-; AIX-PWR10-NEXT: iseleq 3, 4, 3
-; AIX-PWR10-NEXT: cntlzw 3, 3
-; AIX-PWR10-NEXT: rlwinm 3, 3, 27, 31, 31
+; AIX-PWR10-NEXT: xststdcdp cr0, f1, 115
+; AIX-PWR10-NEXT: li r3, 0
+; AIX-PWR10-NEXT: li r4, 1
+; AIX-PWR10-NEXT: iseleq r3, r4, r3
+; AIX-PWR10-NEXT: cntlzw r3, r3
+; AIX-PWR10-NEXT: rlwinm r3, r3, 27, 31, 31
; AIX-PWR10-NEXT: blr
;
; LNXLE64-PWR9-LABEL: _Z16ossIsValidDoubled:
; LNXLE64-PWR9: # %bb.0: # %entry
-; LNXLE64-PWR9-NEXT: xststdcdp 0, 1, 115
-; LNXLE64-PWR9-NEXT: li 3, 0
-; LNXLE64-PWR9-NEXT: li 4, 1
-; LNXLE64-PWR9-NEXT: iseleq 3, 4, 3
-; LNXLE64-PWR9-NEXT: cntlzw 3, 3
-; LNXLE64-PWR9-NEXT: srwi 3, 3, 5
+; LNXLE64-PWR9-NEXT: xststdcdp cr0, f1, 115
+; LNXLE64-PWR9-NEXT: li r3, 0
+; LNXLE64-PWR9-NEXT: li r4, 1
+; LNXLE64-PWR9-NEXT: iseleq r3, r4, r3
+; LNXLE64-PWR9-NEXT: cntlzw r3, r3
+; LNXLE64-PWR9-NEXT: srwi r3, r3, 5
; LNXLE64-PWR9-NEXT: blr
;
; LNXLE64-PWR10-LABEL: _Z16ossIsValidDoubled:
; LNXLE64-PWR10: # %bb.0: # %entry
-; LNXLE64-PWR10-NEXT: xststdcdp 0, 1, 115
-; LNXLE64-PWR10-NEXT: li 3, 0
-; LNXLE64-PWR10-NEXT: li 4, 1
-; LNXLE64-PWR10-NEXT: iseleq 3, 4, 3
-; LNXLE64-PWR10-NEXT: cntlzw 3, 3
-; LNXLE64-PWR10-NEXT: rlwinm 3, 3, 27, 31, 31
+; LNXLE64-PWR10-NEXT: xststdcdp cr0, f1, 115
+; LNXLE64-PWR10-NEXT: li r3, 0
+; LNXLE64-PWR10-NEXT: li r4, 1
+; LNXLE64-PWR10-NEXT: iseleq r3, r4, r3
+; LNXLE64-PWR10-NEXT: cntlzw r3, r3
+; LNXLE64-PWR10-NEXT: rlwinm r3, r3, 27, 31, 31
; LNXLE64-PWR10-NEXT: blr
;
; LNXLE-PWR9-LABEL: _Z16ossIsValidDoubled:
; LNXLE-PWR9: # %bb.0: # %entry
-; LNXLE-PWR9-NEXT: xststdcdp 0, 1, 115
-; LNXLE-PWR9-NEXT: li 3, 0
-; LNXLE-PWR9-NEXT: li 4, 1
-; LNXLE-PWR9-NEXT: iseleq 3, 4, 3
-; LNXLE-PWR9-NEXT: cntlzw 3, 3
-; LNXLE-PWR9-NEXT: rlwinm 3, 3, 27, 31, 31
+; LNXLE-PWR9-NEXT: xststdcdp cr0, f1, 115
+; LNXLE-PWR9-NEXT: li r3, 0
+; LNXLE-PWR9-NEXT: li r4, 1
+; LNXLE-PWR9-NEXT: iseleq r3, r4, r3
+; LNXLE-PWR9-NEXT: cntlzw r3, r3
+; LNXLE-PWR9-NEXT: rlwinm r3, r3, 27, 31, 31
; LNXLE-PWR9-NEXT: blr
;
; LNXLE-PWR10-LABEL: _Z16ossIsValidDoubled:
; LNXLE-PWR10: # %bb.0: # %entry
-; LNXLE-PWR10-NEXT: xststdcdp 0, 1, 115
-; LNXLE-PWR10-NEXT: li 3, 0
-; LNXLE-PWR10-NEXT: li 4, 1
-; LNXLE-PWR10-NEXT: iseleq 3, 4, 3
-; LNXLE-PWR10-NEXT: cntlzw 3, 3
-; LNXLE-PWR10-NEXT: rlwinm 3, 3, 27, 31, 31
+; LNXLE-PWR10-NEXT: xststdcdp cr0, f1, 115
+; LNXLE-PWR10-NEXT: li r3, 0
+; LNXLE-PWR10-NEXT: li r4, 1
+; LNXLE-PWR10-NEXT: iseleq r3, r4, r3
+; LNXLE-PWR10-NEXT: cntlzw r3, r3
+; LNXLE-PWR10-NEXT: rlwinm r3, r3, 27, 31, 31
; LNXLE-PWR10-NEXT: blr
entry:
%test_data_class = tail call i32 @llvm.ppc.test.data.class.f64(double %in, i32 115)
>From 69443cf68040c6946f448c9801e63d9bbf670fa2 Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Thu, 12 Feb 2026 15:30:49 -0500
Subject: [PATCH 3/5] simply the test case
---
.../CodeGen/PowerPC/ppc_test_data_class.ll | 46 ++++++-------------
1 file changed, 13 insertions(+), 33 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll b/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
index 6509baf7e3a48..5b710fb7f5f84 100644
--- a/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=AIX-PWR9 %s
-; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=AIX-PWR10 %s
+; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR10 %s
; RUN: llc -mtriple=powerpc-ibm64-aix7.2.0.0 -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=AIX-PWR9 %s
-; RUN: llc -mtriple=powerpc-ibm64-aix7.2.0.0 -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=AIX-PWR10 %s
+; RUN: llc -mtriple=powerpc-ibm64-aix7.2.0.0 -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR10 %s
; RUN: llc -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 -ppc-asm-full-reg-names< %s | FileCheck --check-prefix=LNXLE64-PWR9 %s
-; RUN: llc -mtriple=powerpc64le-unknown-unknown -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=LNXLE64-PWR10 %s
+; RUN: llc -mtriple=powerpc64le-unknown-unknown -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR10 %s
; RUN: llc -mtriple=powerpcle-unknown-unknown -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=LNXLE-PWR9 %s
-; RUN: llc -mtriple=powerpcle-unknown-unknown -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=LNXLE-PWR10 %s
+; RUN: llc -mtriple=powerpcle-unknown-unknown -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR10 %s
define noundef zeroext i1 @_Z16ossIsValidDoubled(double noundef %in) local_unnamed_addr {
; AIX-PWR9-LABEL: _Z16ossIsValidDoubled:
; AIX-PWR9: # %bb.0: # %entry
@@ -18,15 +18,15 @@ define noundef zeroext i1 @_Z16ossIsValidDoubled(double noundef %in) local_unnam
; AIX-PWR9-NEXT: rlwinm r3, r3, 27, 31, 31
; AIX-PWR9-NEXT: blr
;
-; AIX-PWR10-LABEL: _Z16ossIsValidDoubled:
-; AIX-PWR10: # %bb.0: # %entry
-; AIX-PWR10-NEXT: xststdcdp cr0, f1, 115
-; AIX-PWR10-NEXT: li r3, 0
-; AIX-PWR10-NEXT: li r4, 1
-; AIX-PWR10-NEXT: iseleq r3, r4, r3
-; AIX-PWR10-NEXT: cntlzw r3, r3
-; AIX-PWR10-NEXT: rlwinm r3, r3, 27, 31, 31
-; AIX-PWR10-NEXT: blr
+; PWR10-LABEL: _Z16ossIsValidDoubled:
+; PWR10: # %bb.0: # %entry
+; PWR10-NEXT: xststdcdp cr0, f1, 115
+; PWR10-NEXT: li r3, 0
+; PWR10-NEXT: li r4, 1
+; PWR10-NEXT: iseleq r3, r4, r3
+; PWR10-NEXT: cntlzw r3, r3
+; PWR10-NEXT: rlwinm r3, r3, 27, 31, 31
+; PWR10-NEXT: blr
;
; LNXLE64-PWR9-LABEL: _Z16ossIsValidDoubled:
; LNXLE64-PWR9: # %bb.0: # %entry
@@ -38,16 +38,6 @@ define noundef zeroext i1 @_Z16ossIsValidDoubled(double noundef %in) local_unnam
; LNXLE64-PWR9-NEXT: srwi r3, r3, 5
; LNXLE64-PWR9-NEXT: blr
;
-; LNXLE64-PWR10-LABEL: _Z16ossIsValidDoubled:
-; LNXLE64-PWR10: # %bb.0: # %entry
-; LNXLE64-PWR10-NEXT: xststdcdp cr0, f1, 115
-; LNXLE64-PWR10-NEXT: li r3, 0
-; LNXLE64-PWR10-NEXT: li r4, 1
-; LNXLE64-PWR10-NEXT: iseleq r3, r4, r3
-; LNXLE64-PWR10-NEXT: cntlzw r3, r3
-; LNXLE64-PWR10-NEXT: rlwinm r3, r3, 27, 31, 31
-; LNXLE64-PWR10-NEXT: blr
-;
; LNXLE-PWR9-LABEL: _Z16ossIsValidDoubled:
; LNXLE-PWR9: # %bb.0: # %entry
; LNXLE-PWR9-NEXT: xststdcdp cr0, f1, 115
@@ -57,16 +47,6 @@ define noundef zeroext i1 @_Z16ossIsValidDoubled(double noundef %in) local_unnam
; LNXLE-PWR9-NEXT: cntlzw r3, r3
; LNXLE-PWR9-NEXT: rlwinm r3, r3, 27, 31, 31
; LNXLE-PWR9-NEXT: blr
-;
-; LNXLE-PWR10-LABEL: _Z16ossIsValidDoubled:
-; LNXLE-PWR10: # %bb.0: # %entry
-; LNXLE-PWR10-NEXT: xststdcdp cr0, f1, 115
-; LNXLE-PWR10-NEXT: li r3, 0
-; LNXLE-PWR10-NEXT: li r4, 1
-; LNXLE-PWR10-NEXT: iseleq r3, r4, r3
-; LNXLE-PWR10-NEXT: cntlzw r3, r3
-; LNXLE-PWR10-NEXT: rlwinm r3, r3, 27, 31, 31
-; LNXLE-PWR10-NEXT: blr
entry:
%test_data_class = tail call i32 @llvm.ppc.test.data.class.f64(double %in, i32 115)
%tobool.not = icmp eq i32 %test_data_class, 0
>From f7dae3f86b9f2e45be4e0be8ebf5d987c2219185 Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Thu, 12 Feb 2026 15:35:46 -0500
Subject: [PATCH 4/5] simply the test case
---
.../CodeGen/PowerPC/ppc_test_data_class.ll | 34 +++++++------------
1 file changed, 12 insertions(+), 22 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll b/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
index 5b710fb7f5f84..3f480cc619d5b 100644
--- a/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
@@ -1,22 +1,22 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=AIX-PWR9 %s
+; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR9 %s
; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR10 %s
-; RUN: llc -mtriple=powerpc-ibm64-aix7.2.0.0 -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=AIX-PWR9 %s
+; RUN: llc -mtriple=powerpc-ibm64-aix7.2.0.0 -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR9 %s
; RUN: llc -mtriple=powerpc-ibm64-aix7.2.0.0 -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR10 %s
; RUN: llc -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 -ppc-asm-full-reg-names< %s | FileCheck --check-prefix=LNXLE64-PWR9 %s
; RUN: llc -mtriple=powerpc64le-unknown-unknown -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR10 %s
-; RUN: llc -mtriple=powerpcle-unknown-unknown -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=LNXLE-PWR9 %s
+; RUN: llc -mtriple=powerpcle-unknown-unknown -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR9 %s
; RUN: llc -mtriple=powerpcle-unknown-unknown -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR10 %s
define noundef zeroext i1 @_Z16ossIsValidDoubled(double noundef %in) local_unnamed_addr {
-; AIX-PWR9-LABEL: _Z16ossIsValidDoubled:
-; AIX-PWR9: # %bb.0: # %entry
-; AIX-PWR9-NEXT: xststdcdp cr0, f1, 115
-; AIX-PWR9-NEXT: li r3, 0
-; AIX-PWR9-NEXT: li r4, 1
-; AIX-PWR9-NEXT: iseleq r3, r4, r3
-; AIX-PWR9-NEXT: cntlzw r3, r3
-; AIX-PWR9-NEXT: rlwinm r3, r3, 27, 31, 31
-; AIX-PWR9-NEXT: blr
+; PWR9-LABEL: _Z16ossIsValidDoubled:
+; PWR9: # %bb.0: # %entry
+; PWR9-NEXT: xststdcdp cr0, f1, 115
+; PWR9-NEXT: li r3, 0
+; PWR9-NEXT: li r4, 1
+; PWR9-NEXT: iseleq r3, r4, r3
+; PWR9-NEXT: cntlzw r3, r3
+; PWR9-NEXT: rlwinm r3, r3, 27, 31, 31
+; PWR9-NEXT: blr
;
; PWR10-LABEL: _Z16ossIsValidDoubled:
; PWR10: # %bb.0: # %entry
@@ -37,16 +37,6 @@ define noundef zeroext i1 @_Z16ossIsValidDoubled(double noundef %in) local_unnam
; LNXLE64-PWR9-NEXT: cntlzw r3, r3
; LNXLE64-PWR9-NEXT: srwi r3, r3, 5
; LNXLE64-PWR9-NEXT: blr
-;
-; LNXLE-PWR9-LABEL: _Z16ossIsValidDoubled:
-; LNXLE-PWR9: # %bb.0: # %entry
-; LNXLE-PWR9-NEXT: xststdcdp cr0, f1, 115
-; LNXLE-PWR9-NEXT: li r3, 0
-; LNXLE-PWR9-NEXT: li r4, 1
-; LNXLE-PWR9-NEXT: iseleq r3, r4, r3
-; LNXLE-PWR9-NEXT: cntlzw r3, r3
-; LNXLE-PWR9-NEXT: rlwinm r3, r3, 27, 31, 31
-; LNXLE-PWR9-NEXT: blr
entry:
%test_data_class = tail call i32 @llvm.ppc.test.data.class.f64(double %in, i32 115)
%tobool.not = icmp eq i32 %test_data_class, 0
>From db2104a4a727f2fad32e2e03de24914a82a79e3a Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Fri, 13 Feb 2026 09:43:44 -0500
Subject: [PATCH 5/5] address comment
---
.../CodeGen/PowerPC/ppc_test_data_class.ll | 45 +++++++------------
1 file changed, 17 insertions(+), 28 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll b/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
index 3f480cc619d5b..657b22c18c183 100644
--- a/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
@@ -1,22 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR9 %s
-; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR10 %s
-; RUN: llc -mtriple=powerpc-ibm64-aix7.2.0.0 -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR9 %s
-; RUN: llc -mtriple=powerpc-ibm64-aix7.2.0.0 -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR10 %s
-; RUN: llc -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 -ppc-asm-full-reg-names< %s | FileCheck --check-prefix=LNXLE64-PWR9 %s
-; RUN: llc -mtriple=powerpc64le-unknown-unknown -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR10 %s
-; RUN: llc -mtriple=powerpcle-unknown-unknown -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR9 %s
-; RUN: llc -mtriple=powerpcle-unknown-unknown -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR10 %s
+; RUN: llc -mtriple=powerpc-ibm-aix -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefixes=COMMON,PWR9 %s
+; RUN: llc -mtriple=powerpc-ibm-aix -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR10 %s
+; RUN: llc -mtriple=powerpc64-ibm-aix -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck --check-prefixes=COMMON,PWR9-64 %s
+; RUN: llc -mtriple=powerpc64-ibm-aix -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=PWR10 %s
+
define noundef zeroext i1 @_Z16ossIsValidDoubled(double noundef %in) local_unnamed_addr {
-; PWR9-LABEL: _Z16ossIsValidDoubled:
-; PWR9: # %bb.0: # %entry
-; PWR9-NEXT: xststdcdp cr0, f1, 115
-; PWR9-NEXT: li r3, 0
-; PWR9-NEXT: li r4, 1
-; PWR9-NEXT: iseleq r3, r4, r3
-; PWR9-NEXT: cntlzw r3, r3
-; PWR9-NEXT: rlwinm r3, r3, 27, 31, 31
-; PWR9-NEXT: blr
+; COMMON-LABEL: _Z16ossIsValidDoubled:
+; COMMON: # %bb.0: # %entry
+; COMMON-NEXT: xststdcdp cr0, f1, 115
+; COMMON-NEXT: li r3, 0
+; COMMON-NEXT: li r4, 1
+; COMMON-NEXT: iseleq r3, r4, r3
+; COMMON-NEXT: cntlzw r3, r3
+; PWR9-NEXT: rlwinm r3, r3, 27, 31, 31
+; PWR9-64-NEXT: srwi r3, r3, 5
+; COMMON-NEXT: blr
;
; PWR10-LABEL: _Z16ossIsValidDoubled:
; PWR10: # %bb.0: # %entry
@@ -27,16 +25,8 @@ define noundef zeroext i1 @_Z16ossIsValidDoubled(double noundef %in) local_unnam
; PWR10-NEXT: cntlzw r3, r3
; PWR10-NEXT: rlwinm r3, r3, 27, 31, 31
; PWR10-NEXT: blr
-;
-; LNXLE64-PWR9-LABEL: _Z16ossIsValidDoubled:
-; LNXLE64-PWR9: # %bb.0: # %entry
-; LNXLE64-PWR9-NEXT: xststdcdp cr0, f1, 115
-; LNXLE64-PWR9-NEXT: li r3, 0
-; LNXLE64-PWR9-NEXT: li r4, 1
-; LNXLE64-PWR9-NEXT: iseleq r3, r4, r3
-; LNXLE64-PWR9-NEXT: cntlzw r3, r3
-; LNXLE64-PWR9-NEXT: srwi r3, r3, 5
-; LNXLE64-PWR9-NEXT: blr
+
+
entry:
%test_data_class = tail call i32 @llvm.ppc.test.data.class.f64(double %in, i32 115)
%tobool.not = icmp eq i32 %test_data_class, 0
@@ -44,4 +34,3 @@ entry:
}
declare i32 @llvm.ppc.test.data.class.f64(double, i32 immarg)
-
More information about the llvm-commits
mailing list