[llvm] eb30b5c - [AArch64] Lower SETLE and SETLT vector CondCodes to FCMGT/FCMGE directly.
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 13 00:49:46 PST 2026
Author: David Green
Date: 2026-02-13T08:49:40Z
New Revision: eb30b5cf0b38828090f61f00adb4a7144ddc4231
URL: https://github.com/llvm/llvm-project/commit/eb30b5cf0b38828090f61f00adb4a7144ddc4231
DIFF: https://github.com/llvm/llvm-project/commit/eb30b5cf0b38828090f61f00adb4a7144ddc4231.diff
LOG: [AArch64] Lower SETLE and SETLT vector CondCodes to FCMGT/FCMGE directly.
We previously checked that the compare was NoNan, but the "don't care"
condition codes can be set from known-values as well as nnan instructions.
Lower the vector condition codes directly so that they do not get scalarized
into many scalar instructions.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 11720c314f983..66c22db0491d1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3734,6 +3734,14 @@ static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
CondCode = AArch64CC::MI;
CondCode2 = AArch64CC::GE;
break;
+ case ISD::SETLE:
+ CondCode = AArch64CC::LS;
+ CondCode2 = AArch64CC::AL;
+ break;
+ case ISD::SETLT:
+ CondCode = AArch64CC::MI;
+ CondCode2 = AArch64CC::AL;
+ break;
case ISD::SETUEQ:
case ISD::SETULT:
case ISD::SETULE:
diff --git a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
index 5a7e0be8ae110..9f5592c20277c 100644
--- a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
@@ -4704,36 +4704,13 @@ define <4 x float> @vselect_oge_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x flo
}
define <4 x float> @vselect_olt_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
-; CHECK-SD-LABEL: vselect_olt_knownnnan:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
-; CHECK-SD-NEXT: fmov s3, #1.00000000
-; CHECK-SD-NEXT: mov s4, v0.s[1]
-; CHECK-SD-NEXT: fcmp s4, s3
-; CHECK-SD-NEXT: mov s4, v0.s[2]
-; CHECK-SD-NEXT: csetm w8, lt
-; CHECK-SD-NEXT: fcmp s0, s3
-; CHECK-SD-NEXT: mov s0, v0.s[3]
-; CHECK-SD-NEXT: csetm w9, lt
-; CHECK-SD-NEXT: fcmp s4, s3
-; CHECK-SD-NEXT: fmov s5, w9
-; CHECK-SD-NEXT: mov v5.s[1], w8
-; CHECK-SD-NEXT: csetm w8, lt
-; CHECK-SD-NEXT: fcmp s0, s3
-; CHECK-SD-NEXT: mov v5.s[2], w8
-; CHECK-SD-NEXT: csetm w8, lt
-; CHECK-SD-NEXT: mov v5.s[3], w8
-; CHECK-SD-NEXT: mov v0.16b, v5.16b
-; CHECK-SD-NEXT: bsl v0.16b, v1.16b, v2.16b
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vselect_olt_knownnnan:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: fmov v3.4s, #1.00000000
-; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
-; CHECK-GI-NEXT: fcmgt v0.4s, v3.4s, v0.4s
-; CHECK-GI-NEXT: bsl v0.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vselect_olt_knownnnan:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov v3.4s, #1.00000000
+; CHECK-NEXT: scvtf v0.4s, v0.4s
+; CHECK-NEXT: fcmgt v0.4s, v3.4s, v0.4s
+; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
%b = sitofp <4 x i32> %a to <4 x float>
%c = fcmp olt <4 x float> %b, splat (float 1.0)
%r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
@@ -4741,36 +4718,13 @@ define <4 x float> @vselect_olt_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x flo
}
define <4 x float> @vselect_ole_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
-; CHECK-SD-LABEL: vselect_ole_knownnnan:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
-; CHECK-SD-NEXT: fmov s3, #1.00000000
-; CHECK-SD-NEXT: mov s4, v0.s[1]
-; CHECK-SD-NEXT: fcmp s4, s3
-; CHECK-SD-NEXT: mov s4, v0.s[2]
-; CHECK-SD-NEXT: csetm w8, le
-; CHECK-SD-NEXT: fcmp s0, s3
-; CHECK-SD-NEXT: mov s0, v0.s[3]
-; CHECK-SD-NEXT: csetm w9, le
-; CHECK-SD-NEXT: fcmp s4, s3
-; CHECK-SD-NEXT: fmov s5, w9
-; CHECK-SD-NEXT: mov v5.s[1], w8
-; CHECK-SD-NEXT: csetm w8, le
-; CHECK-SD-NEXT: fcmp s0, s3
-; CHECK-SD-NEXT: mov v5.s[2], w8
-; CHECK-SD-NEXT: csetm w8, le
-; CHECK-SD-NEXT: mov v5.s[3], w8
-; CHECK-SD-NEXT: mov v0.16b, v5.16b
-; CHECK-SD-NEXT: bsl v0.16b, v1.16b, v2.16b
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vselect_ole_knownnnan:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: fmov v3.4s, #1.00000000
-; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
-; CHECK-GI-NEXT: fcmge v0.4s, v3.4s, v0.4s
-; CHECK-GI-NEXT: bsl v0.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vselect_ole_knownnnan:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov v3.4s, #1.00000000
+; CHECK-NEXT: scvtf v0.4s, v0.4s
+; CHECK-NEXT: fcmge v0.4s, v3.4s, v0.4s
+; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
%b = sitofp <4 x i32> %a to <4 x float>
%c = fcmp ole <4 x float> %b, splat (float 1.0)
%r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
@@ -4898,24 +4852,9 @@ define <4 x float> @vselect_uge_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x flo
define <4 x float> @vselect_ult_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
; CHECK-SD-LABEL: vselect_ult_knownnnan:
; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov v3.4s, #1.00000000
; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
-; CHECK-SD-NEXT: fmov s3, #1.00000000
-; CHECK-SD-NEXT: mov s4, v0.s[1]
-; CHECK-SD-NEXT: fcmp s4, s3
-; CHECK-SD-NEXT: mov s4, v0.s[2]
-; CHECK-SD-NEXT: csetm w8, lt
-; CHECK-SD-NEXT: fcmp s0, s3
-; CHECK-SD-NEXT: mov s0, v0.s[3]
-; CHECK-SD-NEXT: csetm w9, lt
-; CHECK-SD-NEXT: fcmp s4, s3
-; CHECK-SD-NEXT: fmov s5, w9
-; CHECK-SD-NEXT: mov v5.s[1], w8
-; CHECK-SD-NEXT: csetm w8, lt
-; CHECK-SD-NEXT: fcmp s0, s3
-; CHECK-SD-NEXT: mov v5.s[2], w8
-; CHECK-SD-NEXT: csetm w8, lt
-; CHECK-SD-NEXT: mov v5.s[3], w8
-; CHECK-SD-NEXT: mov v0.16b, v5.16b
+; CHECK-SD-NEXT: fcmgt v0.4s, v3.4s, v0.4s
; CHECK-SD-NEXT: bsl v0.16b, v1.16b, v2.16b
; CHECK-SD-NEXT: ret
;
@@ -4936,24 +4875,9 @@ define <4 x float> @vselect_ult_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x flo
define <4 x float> @vselect_ule_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
; CHECK-SD-LABEL: vselect_ule_knownnnan:
; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov v3.4s, #1.00000000
; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
-; CHECK-SD-NEXT: fmov s3, #1.00000000
-; CHECK-SD-NEXT: mov s4, v0.s[1]
-; CHECK-SD-NEXT: fcmp s4, s3
-; CHECK-SD-NEXT: mov s4, v0.s[2]
-; CHECK-SD-NEXT: csetm w8, le
-; CHECK-SD-NEXT: fcmp s0, s3
-; CHECK-SD-NEXT: mov s0, v0.s[3]
-; CHECK-SD-NEXT: csetm w9, le
-; CHECK-SD-NEXT: fcmp s4, s3
-; CHECK-SD-NEXT: fmov s5, w9
-; CHECK-SD-NEXT: mov v5.s[1], w8
-; CHECK-SD-NEXT: csetm w8, le
-; CHECK-SD-NEXT: fcmp s0, s3
-; CHECK-SD-NEXT: mov v5.s[2], w8
-; CHECK-SD-NEXT: csetm w8, le
-; CHECK-SD-NEXT: mov v5.s[3], w8
-; CHECK-SD-NEXT: mov v0.16b, v5.16b
+; CHECK-SD-NEXT: fcmge v0.4s, v3.4s, v0.4s
; CHECK-SD-NEXT: bsl v0.16b, v1.16b, v2.16b
; CHECK-SD-NEXT: ret
;
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