[llvm] 8d5a58e - [AArch64] Even more fcmp+select tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 12 23:06:27 PST 2026
Author: David Green
Date: 2026-02-13T07:06:20Z
New Revision: 8d5a58ee8567df51db9c9a3d2c30c2af105ef3fd
URL: https://github.com/llvm/llvm-project/commit/8d5a58ee8567df51db9c9a3d2c30c2af105ef3fd
DIFF: https://github.com/llvm/llvm-project/commit/8d5a58ee8567df51db9c9a3d2c30c2af105ef3fd.diff
LOG: [AArch64] Even more fcmp+select tests. NFC
This time from known bits.
Added:
Modified:
llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
index 896b95ee1363b..5a7e0be8ae110 100644
--- a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
@@ -4657,3 +4657,363 @@ define <4 x float> @vselect_uno_nnan(<4 x float> %a, <4 x float> %b, <4 x float>
%r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
ret <4 x float> %r
}
+
+
+
+
+define <4 x float> @vselect_oeq_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
+; CHECK-LABEL: vselect_oeq_knownnnan:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov v3.4s, #1.00000000
+; CHECK-NEXT: scvtf v0.4s, v0.4s
+; CHECK-NEXT: fcmeq v0.4s, v0.4s, v3.4s
+; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
+ %b = sitofp <4 x i32> %a to <4 x float>
+ %c = fcmp oeq <4 x float> %b, splat (float 1.0)
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ogt_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
+; CHECK-LABEL: vselect_ogt_knownnnan:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov v3.4s, #1.00000000
+; CHECK-NEXT: scvtf v0.4s, v0.4s
+; CHECK-NEXT: fcmgt v0.4s, v0.4s, v3.4s
+; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
+ %b = sitofp <4 x i32> %a to <4 x float>
+ %c = fcmp ogt <4 x float> %b, splat (float 1.0)
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_oge_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
+; CHECK-LABEL: vselect_oge_knownnnan:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov v3.4s, #1.00000000
+; CHECK-NEXT: scvtf v0.4s, v0.4s
+; CHECK-NEXT: fcmge v0.4s, v0.4s, v3.4s
+; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
+ %b = sitofp <4 x i32> %a to <4 x float>
+ %c = fcmp oge <4 x float> %b, splat (float 1.0)
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_olt_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_olt_knownnnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: fmov s3, #1.00000000
+; CHECK-SD-NEXT: mov s4, v0.s[1]
+; CHECK-SD-NEXT: fcmp s4, s3
+; CHECK-SD-NEXT: mov s4, v0.s[2]
+; CHECK-SD-NEXT: csetm w8, lt
+; CHECK-SD-NEXT: fcmp s0, s3
+; CHECK-SD-NEXT: mov s0, v0.s[3]
+; CHECK-SD-NEXT: csetm w9, lt
+; CHECK-SD-NEXT: fcmp s4, s3
+; CHECK-SD-NEXT: fmov s5, w9
+; CHECK-SD-NEXT: mov v5.s[1], w8
+; CHECK-SD-NEXT: csetm w8, lt
+; CHECK-SD-NEXT: fcmp s0, s3
+; CHECK-SD-NEXT: mov v5.s[2], w8
+; CHECK-SD-NEXT: csetm w8, lt
+; CHECK-SD-NEXT: mov v5.s[3], w8
+; CHECK-SD-NEXT: mov v0.16b, v5.16b
+; CHECK-SD-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_olt_knownnnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov v3.4s, #1.00000000
+; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: fcmgt v0.4s, v3.4s, v0.4s
+; CHECK-GI-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ret
+ %b = sitofp <4 x i32> %a to <4 x float>
+ %c = fcmp olt <4 x float> %b, splat (float 1.0)
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ole_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_ole_knownnnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: fmov s3, #1.00000000
+; CHECK-SD-NEXT: mov s4, v0.s[1]
+; CHECK-SD-NEXT: fcmp s4, s3
+; CHECK-SD-NEXT: mov s4, v0.s[2]
+; CHECK-SD-NEXT: csetm w8, le
+; CHECK-SD-NEXT: fcmp s0, s3
+; CHECK-SD-NEXT: mov s0, v0.s[3]
+; CHECK-SD-NEXT: csetm w9, le
+; CHECK-SD-NEXT: fcmp s4, s3
+; CHECK-SD-NEXT: fmov s5, w9
+; CHECK-SD-NEXT: mov v5.s[1], w8
+; CHECK-SD-NEXT: csetm w8, le
+; CHECK-SD-NEXT: fcmp s0, s3
+; CHECK-SD-NEXT: mov v5.s[2], w8
+; CHECK-SD-NEXT: csetm w8, le
+; CHECK-SD-NEXT: mov v5.s[3], w8
+; CHECK-SD-NEXT: mov v0.16b, v5.16b
+; CHECK-SD-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_ole_knownnnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov v3.4s, #1.00000000
+; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: fcmge v0.4s, v3.4s, v0.4s
+; CHECK-GI-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ret
+ %b = sitofp <4 x i32> %a to <4 x float>
+ %c = fcmp ole <4 x float> %b, splat (float 1.0)
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_one_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_one_knownnnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov v3.4s, #1.00000000
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v3.4s
+; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_one_knownnnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov v3.4s, #1.00000000
+; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: fcmgt v4.4s, v0.4s, v3.4s
+; CHECK-GI-NEXT: fcmgt v0.4s, v3.4s, v0.4s
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v4.16b
+; CHECK-GI-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ret
+ %b = sitofp <4 x i32> %a to <4 x float>
+ %c = fcmp one <4 x float> %b, splat (float 1.0)
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ord_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_ord_knownnnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v0.4s
+; CHECK-SD-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_ord_knownnnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov v3.4s, #1.00000000
+; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: fcmge v4.4s, v0.4s, v3.4s
+; CHECK-GI-NEXT: fcmgt v0.4s, v3.4s, v0.4s
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v4.16b
+; CHECK-GI-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ret
+ %b = sitofp <4 x i32> %a to <4 x float>
+ %c = fcmp ord <4 x float> %b, splat (float 1.0)
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ueq_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_ueq_knownnnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov v3.4s, #1.00000000
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v3.4s
+; CHECK-SD-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_ueq_knownnnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov v3.4s, #1.00000000
+; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: fcmgt v4.4s, v0.4s, v3.4s
+; CHECK-GI-NEXT: fcmgt v0.4s, v3.4s, v0.4s
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v4.16b
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ret
+ %b = sitofp <4 x i32> %a to <4 x float>
+ %c = fcmp ueq <4 x float> %b, splat (float 1.0)
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ugt_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_ugt_knownnnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov v3.4s, #1.00000000
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: fcmgt v0.4s, v0.4s, v3.4s
+; CHECK-SD-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_ugt_knownnnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov v3.4s, #1.00000000
+; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: fcmge v0.4s, v3.4s, v0.4s
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ret
+ %b = sitofp <4 x i32> %a to <4 x float>
+ %c = fcmp ugt <4 x float> %b, splat (float 1.0)
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_uge_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_uge_knownnnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov v3.4s, #1.00000000
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: fcmge v0.4s, v0.4s, v3.4s
+; CHECK-SD-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_uge_knownnnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov v3.4s, #1.00000000
+; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: fcmgt v0.4s, v3.4s, v0.4s
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ret
+ %b = sitofp <4 x i32> %a to <4 x float>
+ %c = fcmp uge <4 x float> %b, splat (float 1.0)
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ult_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_ult_knownnnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: fmov s3, #1.00000000
+; CHECK-SD-NEXT: mov s4, v0.s[1]
+; CHECK-SD-NEXT: fcmp s4, s3
+; CHECK-SD-NEXT: mov s4, v0.s[2]
+; CHECK-SD-NEXT: csetm w8, lt
+; CHECK-SD-NEXT: fcmp s0, s3
+; CHECK-SD-NEXT: mov s0, v0.s[3]
+; CHECK-SD-NEXT: csetm w9, lt
+; CHECK-SD-NEXT: fcmp s4, s3
+; CHECK-SD-NEXT: fmov s5, w9
+; CHECK-SD-NEXT: mov v5.s[1], w8
+; CHECK-SD-NEXT: csetm w8, lt
+; CHECK-SD-NEXT: fcmp s0, s3
+; CHECK-SD-NEXT: mov v5.s[2], w8
+; CHECK-SD-NEXT: csetm w8, lt
+; CHECK-SD-NEXT: mov v5.s[3], w8
+; CHECK-SD-NEXT: mov v0.16b, v5.16b
+; CHECK-SD-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_ult_knownnnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov v3.4s, #1.00000000
+; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: fcmge v0.4s, v0.4s, v3.4s
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ret
+ %b = sitofp <4 x i32> %a to <4 x float>
+ %c = fcmp ult <4 x float> %b, splat (float 1.0)
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ule_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_ule_knownnnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: fmov s3, #1.00000000
+; CHECK-SD-NEXT: mov s4, v0.s[1]
+; CHECK-SD-NEXT: fcmp s4, s3
+; CHECK-SD-NEXT: mov s4, v0.s[2]
+; CHECK-SD-NEXT: csetm w8, le
+; CHECK-SD-NEXT: fcmp s0, s3
+; CHECK-SD-NEXT: mov s0, v0.s[3]
+; CHECK-SD-NEXT: csetm w9, le
+; CHECK-SD-NEXT: fcmp s4, s3
+; CHECK-SD-NEXT: fmov s5, w9
+; CHECK-SD-NEXT: mov v5.s[1], w8
+; CHECK-SD-NEXT: csetm w8, le
+; CHECK-SD-NEXT: fcmp s0, s3
+; CHECK-SD-NEXT: mov v5.s[2], w8
+; CHECK-SD-NEXT: csetm w8, le
+; CHECK-SD-NEXT: mov v5.s[3], w8
+; CHECK-SD-NEXT: mov v0.16b, v5.16b
+; CHECK-SD-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_ule_knownnnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov v3.4s, #1.00000000
+; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: fcmgt v0.4s, v0.4s, v3.4s
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ret
+ %b = sitofp <4 x i32> %a to <4 x float>
+ %c = fcmp ule <4 x float> %b, splat (float 1.0)
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_une_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_une_knownnnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov v3.4s, #1.00000000
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v3.4s
+; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_une_knownnnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov v3.4s, #1.00000000
+; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: fcmeq v0.4s, v0.4s, v3.4s
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ret
+ %b = sitofp <4 x i32> %a to <4 x float>
+ %c = fcmp une <4 x float> %b, splat (float 1.0)
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_uno_knownnnan(<4 x i32> %a, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_uno_knownnnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v0.4s
+; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_uno_knownnnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov v3.4s, #1.00000000
+; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: fcmge v4.4s, v0.4s, v3.4s
+; CHECK-GI-NEXT: fcmgt v0.4s, v3.4s, v0.4s
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v4.16b
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ret
+ %b = sitofp <4 x i32> %a to <4 x float>
+ %c = fcmp uno <4 x float> %b, splat (float 1.0)
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
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