[llvm] [GlobalISel] Add G_UDIV/G_SDIV computeKnownBits (PR #181307)
Alex Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 12 20:50:35 PST 2026
https://github.com/aeft created https://github.com/llvm/llvm-project/pull/181307
Code ported from `SelectionDAG::computeKnownBits`.
Related: #150515
>From d55c40a09af1f146aef7662946b10465d5b6d5a4 Mon Sep 17 00:00:00 2001
From: Alex Wang <yesterda9 at gmail.com>
Date: Thu, 12 Feb 2026 20:39:36 -0800
Subject: [PATCH] [GlobalISel] Add G_UDIV/G_SDIV computeKnownBits
Code ported from SelectionDAG::computeKnownBits.
---
.../CodeGen/GlobalISel/GISelValueTracking.cpp | 18 +++++
.../AArch64/GlobalISel/knownbits-sdiv.mir | 67 +++++++++++++++++++
.../AArch64/GlobalISel/knownbits-udiv.mir | 55 +++++++++++++++
3 files changed, 140 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sdiv.mir
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/knownbits-udiv.mir
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index fce06dfde0edc..6fe91406ce958 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -368,6 +368,24 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
Known = KnownBits::mulhs(Known, Known2);
break;
}
+ case TargetOpcode::G_UDIV: {
+ computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
+ Depth + 1);
+ computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
+ Depth + 1);
+ Known = KnownBits::udiv(Known, Known2,
+ MI.getFlag(MachineInstr::MIFlag::IsExact));
+ break;
+ }
+ case TargetOpcode::G_SDIV: {
+ computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
+ Depth + 1);
+ computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
+ Depth + 1);
+ Known = KnownBits::sdiv(Known, Known2,
+ MI.getFlag(MachineInstr::MIFlag::IsExact));
+ break;
+ }
case TargetOpcode::G_SELECT: {
computeKnownBitsMin(MI.getOperand(2).getReg(), MI.getOperand(3).getReg(),
Known, DemandedElts, Depth + 1);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sdiv.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sdiv.mir
new file mode 100644
index 0000000000000..7b315205bc2e8
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sdiv.mir
@@ -0,0 +1,67 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=aarch64 -passes='print<gisel-value-tracking>' -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name: Cst
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @Cst
+ ; CHECK-NEXT: %0:_ KnownBits:01100100 SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5
+ ; CHECK-NEXT: %2:_ KnownBits:000????? SignBits:3
+ %0:_(s8) = G_CONSTANT i8 100
+ %1:_(s8) = G_CONSTANT i8 4
+ %2:_(s8) = G_SDIV %0, %1
+...
+---
+name: PartialKnown
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @PartialKnown
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:00001111 SignBits:4
+ ; CHECK-NEXT: %2:_ KnownBits:0000???? SignBits:4
+ ; CHECK-NEXT: %3:_ KnownBits:00000100 SignBits:5
+ ; CHECK-NEXT: %4:_ KnownBits:000000?? SignBits:6
+ %0:_(s8) = G_IMPLICIT_DEF
+ %1:_(s8) = G_CONSTANT i8 15
+ %2:_(s8) = G_AND %0, %1
+ %3:_(s8) = G_CONSTANT i8 4
+ %4:_(s8) = G_SDIV %2, %3
+...
+---
+name: Exact
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @Exact
+ ; CHECK-NEXT: %0:_ KnownBits:00001100 SignBits:4
+ ; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5
+ ; CHECK-NEXT: %2:_ KnownBits:000000?1 SignBits:6
+ %0:_(s8) = G_CONSTANT i8 12
+ %1:_(s8) = G_CONSTANT i8 4
+ %2:_(s8) = exact G_SDIV %0, %1
+...
+---
+name: NegDividend
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @NegDividend
+ ; CHECK-NEXT: %0:_ KnownBits:11110000 SignBits:4
+ ; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5
+ ; CHECK-NEXT: %2:_ KnownBits:111111?? SignBits:6
+ %0:_(s8) = G_CONSTANT i8 -16
+ %1:_(s8) = G_CONSTANT i8 4
+ %2:_(s8) = G_SDIV %0, %1
+...
+---
+name: Unknown
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @Unknown
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s8) = COPY $b1
+ %2:_(s8) = G_SDIV %0, %1
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-udiv.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-udiv.mir
new file mode 100644
index 0000000000000..dfbcd3f3c6188
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-udiv.mir
@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=aarch64 -passes='print<gisel-value-tracking>' -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name: Cst
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @Cst
+ ; CHECK-NEXT: %0:_ KnownBits:01100100 SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5
+ ; CHECK-NEXT: %2:_ KnownBits:000????? SignBits:3
+ %0:_(s8) = G_CONSTANT i8 100
+ %1:_(s8) = G_CONSTANT i8 4
+ %2:_(s8) = G_UDIV %0, %1
+...
+---
+name: PartialKnown
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @PartialKnown
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:00001111 SignBits:4
+ ; CHECK-NEXT: %2:_ KnownBits:0000???? SignBits:4
+ ; CHECK-NEXT: %3:_ KnownBits:00000100 SignBits:5
+ ; CHECK-NEXT: %4:_ KnownBits:000000?? SignBits:6
+ %0:_(s8) = G_IMPLICIT_DEF
+ %1:_(s8) = G_CONSTANT i8 15
+ %2:_(s8) = G_AND %0, %1
+ %3:_(s8) = G_CONSTANT i8 4
+ %4:_(s8) = G_UDIV %2, %3
+...
+---
+name: Exact
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @Exact
+ ; CHECK-NEXT: %0:_ KnownBits:00001100 SignBits:4
+ ; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5
+ ; CHECK-NEXT: %2:_ KnownBits:000000?1 SignBits:6
+ %0:_(s8) = G_CONSTANT i8 12
+ %1:_(s8) = G_CONSTANT i8 4
+ %2:_(s8) = exact G_UDIV %0, %1
+...
+---
+name: Unknown
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @Unknown
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s8) = COPY $b1
+ %2:_(s8) = G_UDIV %0, %1
+...
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