[llvm] [AMDGPU] Fix handling of setting register classes in MFMA scheduler rewrite stage (PR #181047)

[Tony Linthicum via llvm-commits]

tlinthic wrote:

> You probably need to use mir to get a manageable sized test. You can also try looking at some of the other pressure stress tests. They usually do volatile loads and stores of enough wide vectors, or asm

Got it.  I'll have an updated test hopefully sometime next week.

https://github.com/llvm/llvm-project/pull/181047