[llvm] [SystemZ][z/OS] Migrate most test case to use HLASM syntax (PR #181222)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 12 11:55:26 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-systemz
Author: Kai Nacke (redstar)
<details>
<summary>Changes</summary>
This PR migrates all but one test case to use HLASM syntax. It also flips the default for the command line option, making HLASM output the default.
The missing test case requires some more support in the HLASM streamer, which I will add separately.
---
Patch is 42.96 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/181222.diff
29 Files Affected:
- (modified) llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/call-zos-01.ll (+20-20)
- (modified) llvm/test/CodeGen/SystemZ/call-zos-02.ll (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/call-zos-i128.ll (+2-2)
- (modified) llvm/test/CodeGen/SystemZ/call-zos-vararg.ll (+19-20)
- (modified) llvm/test/CodeGen/SystemZ/llvm.sincos.ll (+18-13)
- (modified) llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll (+15-15)
- (modified) llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll (+16-12)
- (modified) llvm/test/CodeGen/SystemZ/zos-ada.ll (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/zos-alias-unsupported.ll (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/zos-dwarf.ll (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/zos-frameaddr.ll (+4-4)
- (modified) llvm/test/CodeGen/SystemZ/zos-func-alias.ll (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/zos-hlasm-out.ll (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/zos-intrinsics.ll (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/zos-jumptable.ll (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/zos-landingpad.ll (+13-9)
- (modified) llvm/test/CodeGen/SystemZ/zos-lower-constant.ll (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/zos-no-eh-label.ll (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/zos-ppa1.ll (+42-22)
- (modified) llvm/test/CodeGen/SystemZ/zos-ppa2.ll (+34-25)
- (modified) llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll (+60-57)
- (modified) llvm/test/CodeGen/SystemZ/zos-ret-addr.ll (+3-3)
- (modified) llvm/test/CodeGen/SystemZ/zos-simple-test.ll (+1-2)
- (modified) llvm/test/CodeGen/SystemZ/zos-stackpointer.ll (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/zos-symbol-1.ll (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/zos-symbol-2.ll (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/zos_sinit.ll (+1-1)
``````````diff
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
index faef5bb926780..4356f7ad05121 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
@@ -41,7 +41,7 @@ using namespace llvm;
// z/OS
static cl::opt<bool> GNUAsOnzOSCL("emit-gnuas-syntax-on-zos",
cl::desc("Emit GNU Assembly Syntax on z/OS."),
- cl::init(true));
+ cl::init(false));
const unsigned SystemZMC::GR32Regs[16] = {
SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-01.ll b/llvm/test/CodeGen/SystemZ/call-zos-01.ll
index 7ad1e4c4679eb..7a2fb3f2dfc49 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-01.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-01.ll
@@ -2,14 +2,14 @@
;
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
-; CHECK-LABEL: call_char:
+; CHECK-LABEL: call_char DS 0H
; CHECK: lghi 1,8
define i8 @call_char(){
%retval = call i8 (i8) @pass_char(i8 8)
ret i8 %retval
}
-; CHECK-LABEL: call_short:
+; CHECK-LABEL: call_short DS 0H
; CHECK: lghi 1,16
define i16 @call_short() {
entry:
@@ -17,7 +17,7 @@ entry:
ret i16 %retval
}
-; CHECK-LABEL: call_int:
+; CHECK-LABEL: call_int DS 0H
; CHECK: lghi 1,32
; CHECK: lghi 2,33
define i32 @call_int() {
@@ -26,7 +26,7 @@ entry:
ret i32 %retval
}
-; CHECK-LABEL: call_long:
+; CHECK-LABEL: call_long DS 0H
; CHECK: lghi 1,64
; CHECK: lghi 2,65
; CHECK: lghi 3,66
@@ -36,7 +36,7 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_ptr:
+; CHECK-LABEL: call_ptr DS 0H
; CHECK: lgr 1,2
define i32 @call_ptr(ptr %p1, ptr %p2) {
entry:
@@ -44,7 +44,7 @@ entry:
ret i32 %retval
}
-; CHECK-LABEL: call_integrals:
+; CHECK-LABEL: call_integrals DS 0H
; CHECK: lghi 1,64
; CHECK: lghi 2,32
; CHECK: lghi 3,16
@@ -54,28 +54,28 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: pass_char:
+; CHECK-LABEL: pass_char DS 0H
; CHECK: lgr 3,1
define signext i8 @pass_char(i8 signext %arg) {
entry:
ret i8 %arg
}
-; CHECK-LABEL: pass_short:
+; CHECK-LABEL: pass_short DS 0H
; CHECK: lgr 3,1
define signext i16 @pass_short(i16 signext %arg) {
entry:
ret i16 %arg
}
-; CHECK-LABEL: pass_int:
+; CHECK-LABEL: pass_int DS 0H
; CHECK: lgr 3,2
define signext i32 @pass_int(i32 signext %arg0, i32 signext %arg1) {
entry:
ret i32 %arg1
}
-; CHECK-LABEL: pass_long:
+; CHECK-LABEL: pass_long DS 0H
; CHECK: agr 1,2
; CHECK: agr 3,1
define signext i64 @pass_long(i64 signext %arg0, i64 signext %arg1, i64 signext %arg2) {
@@ -85,7 +85,7 @@ entry:
ret i64 %M
}
-; CHECK-LABEL: pass_integrals0:
+; CHECK-LABEL: pass_integrals0 DS 0H
; CHECK: ag 2,2200(4)
; CHECK-NEXT: lgr 3,2
define signext i64 @pass_integrals0(i64 signext %arg0, i32 signext %arg1, i16 signext %arg2, i64 signext %arg3) {
@@ -95,7 +95,7 @@ entry:
ret i64 %M
}
-; CHECK-LABEL: call_float:
+; CHECK-LABEL: call_float DS 0H
; CHECK: le 0,0({{[0-9]}})
define float @call_float() {
entry:
@@ -103,7 +103,7 @@ entry:
ret float %ret
}
-; CHECK-LABEL: call_double:
+; CHECK-LABEL: call_double DS 0H
; CHECK: larl [[GENREG:[0-9]+]],L#{{CPI[0-9]+_[0-9]+}}
; CHECK-NEXT: ld 0,0([[GENREG]])
define double @call_double() {
@@ -112,7 +112,7 @@ entry:
ret double %ret
}
-; CHECK-LABEL: call_longdouble:
+; CHECK-LABEL: call_longdouble DS 0H
; CHECK: larl [[GENREG:[0-9]+]],L#{{CPI[0-9]+_[0-9]+}}
; CHECK-NEXT: ld 0,0([[GENREG]])
; CHECK-NEXT: ld 2,8([[GENREG]])
@@ -122,7 +122,7 @@ entry:
ret fp128 %ret
}
-; CHECK-LABEL: call_floats0
+; CHECK-LABEL: call_floats0 DS 0H
; CHECK: larl [[GENREG:[0-9]+]],L#{{CPI[0-9]+_[0-9]+}}
; CHECK-NEXT: ld 1,0([[GENREG]])
; CHECK-NEXT: ld 3,8([[GENREG]])
@@ -135,7 +135,7 @@ entry:
ret i64 %ret
}
-; CHECK-LABEL: call_floats1
+; CHECK-LABEL: call_floats1 DS 0H
; CHECK: lxr 1,0
; CHECK: ldr 0,4
; CHECK: lxr 4,1
@@ -145,7 +145,7 @@ entry:
ret i64 %ret
}
-; CHECK-LABEL: pass_float:
+; CHECK-LABEL: pass_float DS 0H
; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
; CHECK: aeb 0,0(1)
define float @pass_float(float %arg) {
@@ -154,7 +154,7 @@ entry:
ret float %X
}
-; CHECK-LABEL: pass_double:
+; CHECK-LABEL: pass_double DS 0H
; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
; CHECK: adb 0,0(1)
define double @pass_double(double %arg) {
@@ -163,7 +163,7 @@ entry:
ret double %X
}
-; CHECK-LABEL: pass_longdouble
+; CHECK-LABEL: pass_longdouble DS 0H
; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
; CHECK: lxdb 1,0(1)
; CHECK: axbr 0,1
@@ -173,7 +173,7 @@ entry:
ret fp128 %X
}
-; CHECK-LABEL: pass_floats0
+; CHECK-LABEL: pass_floats0 DS 0H
; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
; CHECK: axbr 0,4
; CHECK: axbr 1,0
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-02.ll b/llvm/test/CodeGen/SystemZ/call-zos-02.ll
index a7f600ae99db0..4f1013fc8974d 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-02.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-02.ll
@@ -1,4 +1,4 @@
-; RUN: llc --mtriple=s390x-ibm-zos --show-mc-encoding < %s | FileCheck %s
+; RUN: llc --mtriple=s390x-ibm-zos --show-mc-encoding -emit-gnuas-syntax-on-zos=1 < %s | FileCheck %s
define internal signext i32 @caller() {
entry:
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-i128.ll b/llvm/test/CodeGen/SystemZ/call-zos-i128.ll
index 98c3d84bc8bf9..c12e26184f068 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-i128.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-i128.ll
@@ -2,7 +2,7 @@
;
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z13 | FileCheck %s
-; CHECK-LABEL: call_i128:
+; CHECK-LABEL: call_i128 DS 0H
; CHECK-DAG: larl 1,L#CPI0_0
; CHECK-DAG: vl 0,0(1),3
; CHECK-DAG: vst 0,2256(4),3
@@ -19,7 +19,7 @@ entry:
ret i128 %retval
}
-; CHECK-LABEL: pass_i128:
+; CHECK-LABEL: pass_i128 DS 0H
; CHECK: vl 0,0(3),3
; CHECK: vl 1,0(2),3
; CHECK: vaq 0,1,0
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll b/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
index 72f4d79610e0e..147fbe63f5af4 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
@@ -1,7 +1,7 @@
; Test passing variable argument lists in 64-bit calls on z/OS.
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z14 | FileCheck %s -check-prefix=ARCH12
-; CHECK-LABEL: call_vararg_double0:
+; CHECK-LABEL: call_vararg_double0 DS 0H
; CHECK: stmg 6,7,1872(4)
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: lg 6,8(5)
@@ -21,7 +21,7 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_double1:
+; CHECK-LABEL: call_vararg_double1 DS 0H
; CHECK: stmg 6,7,1872(4)
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: llihf 0,1074118262
@@ -44,7 +44,7 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_double2:
+; CHECK-LABEL: call_vararg_double2 DS 0H
; CHECK: stmg 6,7,1872(4)
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: lg 6,24(5)
@@ -63,7 +63,7 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_double3:
+; CHECK-LABEL: call_vararg_double3 DS 0H
; CHECK: stmg 6,7,1872(4)
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: llihf 0,1072703839
@@ -89,7 +89,7 @@ entry:
}
;; TODO: The extra COPY after LGDR is unnecessary (machine-scheduler introduces the overlap).
-; CHECK-LABEL: call_vararg_both0:
+; CHECK-LABEL: call_vararg_both0 DS 0H
; CHECK: stmg 6,7,1872(4)
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: lg 6,40(5)
@@ -107,7 +107,7 @@ define i64 @call_vararg_both0(i64 %arg0, double %arg1) {
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_long_double0:
+; CHECK-LABEL: call_vararg_long_double0 DS 0H
; CHECK: stmg 6,7,1872(4)
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: larl 1,L#CPI5_0
@@ -131,7 +131,7 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_long_double1:
+; CHECK-LABEL: call_vararg_long_double1 DS 0H
; CHECK: stmg 6,7,1872(4)
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: lg 6,8(5)
@@ -152,8 +152,7 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_long_double2
-; CHECK-LABEL: call_vararg_long_double2:
+; CHECK-LABEL: call_vararg_long_double2 DS 0H
; CHECK: stmg 6,7,1872(4)
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: std 4,2208(4)
@@ -176,7 +175,7 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_long_double3:
+; CHECK-LABEL: call_vararg_long_double3 DS 0H
; CHECK: stmg 6,7,1872(4)
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: lg 6,40(5)
@@ -194,7 +193,7 @@ entry:
ret i64 %retval
}
-; ARCH12-LABEL: call_vec_vararg_test0
+; ARCH12-LABEL: call_vec_vararg_test0 DS 0H
; ARCH12: vlgvg 3,24,1
; ARCH12: vlgvg 2,24,0
; ARCH12: lghi 1,1
@@ -203,7 +202,7 @@ define void @call_vec_vararg_test0(<2 x double> %v) {
ret void
}
-; ARCH12-LABEL: call_vec_vararg_test1
+; ARCH12-LABEL: call_vec_vararg_test1 DS 0H
; ARCH12: larl 1,L#CPI10_0
; ARCH12: vl 0,0(1),3
; ARCH12: vlgvg 3,24,0
@@ -215,7 +214,7 @@ define void @call_vec_vararg_test1(<4 x i32> %v, <2 x i64> %w) {
ret void
}
-; ARCH12-LABEL: call_vec_char_vararg_straddle
+; ARCH12-LABEL: call_vec_char_vararg_straddle DS 0H
; ARCH12: vlgvg 3,24,0
; ARCH12: lghi 1,1
; ARCH12: lghi 2,2
@@ -225,7 +224,7 @@ define void @call_vec_char_vararg_straddle(<16 x i8> %v) {
ret void
}
-; ARCH12-LABEL: call_vec_short_vararg_straddle
+; ARCH12-LABEL: call_vec_short_vararg_straddle DS 0H
; ARCH12: vlgvg 3,24,0
; ARCH12: lghi 1,1
; ARCH12: lghi 2,2
@@ -235,7 +234,7 @@ define void @call_vec_short_vararg_straddle(<8 x i16> %v) {
ret void
}
-; ARCH12-LABEL: call_vec_int_vararg_straddle
+; ARCH12-LABEL: call_vec_int_vararg_straddle DS 0H
; ARCH12: vlgvg 3,24,0
; ARCH12: lghi 1,1
; ARCH12: lghi 2,2
@@ -245,7 +244,7 @@ define void @call_vec_int_vararg_straddle(<4 x i32> %v) {
ret void
}
-; ARCH12-LABEL: call_vec_double_vararg_straddle
+; ARCH12-LABEL: call_vec_double_vararg_straddle DS 0H
; ARCH12: vlgvg 3,24,0
; ARCH12: lghi 1,1
; ARCH12: lghi 2,2
@@ -255,7 +254,7 @@ define void @call_vec_double_vararg_straddle(<2 x double> %v) {
ret void
}
-; CHECK-LABEL: call_vararg_integral0:
+; CHECK-LABEL: call_vararg_integral0 DS 0H
; CHECK: stmg 6,7,1872(4)
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: lg 0,2392(4)
@@ -273,7 +272,7 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_float0:
+; CHECK-LABEL: call_vararg_float0 DS 0H
; CHECK: stmg 6,7,1872(4)
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: lg 6,24(5)
@@ -291,7 +290,7 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_float1:
+; CHECK-LABEL: call_vararg_float1 DS 0H
; CHECK: stmg 6,7,1872(4)
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: lg 6,72(5)
@@ -325,7 +324,7 @@ entry:
; return ret;
; }
;
-; CHECK-LABEL: pass_vararg:
+; CHECK-LABEL: pass_vararg DS 0H
; CHECK: stmg 6,7,1904(4)
; CHECK-NEXT: aghi 4,-160
; CHECK-NEXT: stg 2,2344(4)
diff --git a/llvm/test/CodeGen/SystemZ/llvm.sincos.ll b/llvm/test/CodeGen/SystemZ/llvm.sincos.ll
index e47759b188296..964f9b696c1dd 100644
--- a/llvm/test/CodeGen/SystemZ/llvm.sincos.ll
+++ b/llvm/test/CodeGen/SystemZ/llvm.sincos.ll
@@ -183,19 +183,24 @@ define { <2 x fp128>, <2 x fp128> } @test_sincos_v2f128(<2 x fp128> %a) #0 {
ret { <2 x fp128>, <2 x fp128> } %result
}
-
-; ZOS: .quad RD(@@FSIN at B) * Offset 0 function descriptor of @@FSIN at B
-; ZOS: .quad VD(@@FSIN at B)
-; ZOS: .quad RD(@@FCOS at B) * Offset 16 function descriptor of @@FCOS at B
-; ZOS: .quad VD(@@FCOS at B)
-; ZOS: .quad RD(@@SSIN at B) * Offset 32 function descriptor of @@SSIN at B
-; ZOS: .quad VD(@@SSIN at B)
-; ZOS: .quad RD(@@SCOS at B) * Offset 48 function descriptor of @@SCOS at B
-; ZOS: .quad VD(@@SCOS at B)
-; ZOS: .quad RD(@@LSIN at B) * Offset 64 function descriptor of @@LSIN at B
-; ZOS: .quad VD(@@LSIN at B)
-; ZOS: .quad RD(@@LCOS at B) * Offset 80 function descriptor of @@LCOS at B
-; ZOS: .quad VD(@@LCOS at B)
+; ZOS: * Offset 0 function descriptor of @@FSIN at B
+; ZOS: DC RD(@@FSIN at B)
+; ZOS: DC VD(@@FSIN at B)
+; ZOS: * Offset 16 function descriptor of @@FCOS at B
+; ZOS: DC RD(@@FCOS at B)
+; ZOS: DC VD(@@FCOS at B)
+; ZOS: * Offset 32 function descriptor of @@SSIN at B
+; ZOS: DC RD(@@SSIN at B)
+; ZOS: DC VD(@@SSIN at B)
+; ZOS: * Offset 48 function descriptor of @@SCOS at B
+; ZOS: DC RD(@@SCOS at B)
+; ZOS: DC VD(@@SCOS at B)
+; ZOS: * Offset 64 function descriptor of @@LSIN at B
+; ZOS: DC RD(@@LSIN at B)
+; ZOS: DC VD(@@LSIN at B)
+; ZOS: * Offset 80 function descriptor of @@LCOS at B
+; ZOS: DC RD(@@LCOS at B)
+; ZOS: DC VD(@@LCOS at B)
attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll b/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
index a95f68b5e118d..ddd6850e54406 100644
--- a/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
+++ b/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
@@ -103,7 +103,7 @@ declare void @use_foo(ptr)
define void @ptr32_to_ptr(ptr %f, ptr addrspace(1) %i) {
entry:
-; CHECK-LABEL: ptr32_to_ptr:
+; CHECK-LABEL: ptr32_to_ptr DS 0H
; CHECK: llgtr 0,2
; CHECK-NEXT: stg 0,8(1)
%0 = addrspacecast ptr addrspace(1) %i to ptr
@@ -115,7 +115,7 @@ entry:
define void @ptr_to_ptr32(ptr %f, ptr %i) {
entry:
-; CHECK-LABEL: ptr_to_ptr32:
+; CHECK-LABEL: ptr_to_ptr32 DS 0H
; CHECK: nilh 2,32767
; CHECK-NEXT: st 2,0(1)
%0 = addrspacecast ptr %i to ptr addrspace(1)
@@ -127,7 +127,7 @@ entry:
define void @ptr32_to_ptr32(ptr %f, ptr addrspace(1) %i) {
entry:
-; CHECK-LABEL: ptr32_to_ptr32:
+; CHECK-LABEL: ptr32_to_ptr32 DS 0H
; CHECK: st 2,0(1)
%p32 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 0
store ptr addrspace(1) %i, ptr %p32, align 8
@@ -136,7 +136,7 @@ entry:
}
define void @ptr_to_ptr(ptr %f, ptr %i) {
-; CHECK-LABEL: ptr_to_ptr:
+; CHECK-LABEL: ptr_to_ptr DS 0H
; CHECK: stg 2,8(1)
%p64 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 1
store ptr %i, ptr %p64, align 8
@@ -146,7 +146,7 @@ define void @ptr_to_ptr(ptr %f, ptr %i) {
define void @test_indexing(ptr %f) {
entry:
-; CHECK-LABEL: test_indexing:
+; CHECK-LABEL: test_indexing DS 0H
; CHECK: l 0,1032
; CHECK: llgtr 0,0
; CHECK: stg 0,16(1)
@@ -160,7 +160,7 @@ entry:
define void @test_indexing_2(ptr %f) {
entry:
-; CHECK-LABEL: test_indexing_2:
+; CHECK-LABEL: test_indexing_2 DS 0H
; CHECK: lhi 0,16
; CHECK-NEXT: a 0,1032
; CHECK-NEXT: llgtr 2,0
@@ -181,7 +181,7 @@ entry:
define ptr @test_misc() {
entry:
-; CHECK-LABEL: test_misc:
+; CHECK-LABEL: test_misc DS 0H
; CHECK: lhi 0,88
; CHECK-NEXT: a 0,1208
; CHECK-NEXT: llgtr 1,0
@@ -204,7 +204,7 @@ entry:
define ptr addrspace(1) @test_misc_2() {
entry:
-; CHECK-LABEL: test_misc_2:
+; CHECK-LABEL: test_misc_2 DS 0H
; CHECK: lhi 0,544
; CHECK: a 0,16
; CHECK: llgtr 1,0
@@ -221,7 +221,7 @@ entry:
define zeroext i16 @test_misc_3() {
entry:
-; CHECK-LABEL: test_misc_3:
+; CHECK-LABEL: test_misc_3 DS 0H
; CHECK: a 0,548
; CHECK-NEXT: llgtr 1,0
; CHECK-NEXT: llgh 3,0(1)
@@ -235,7 +235,7 @@ entry:
define signext i32 @test_misc_4() {
entry:
-; CHECK-LABEL: test_misc_4:
+; CHECK-LABEL: test_misc_4 DS 0H
; CHECK: lhi 0,88
; CHECK-NEXT: a 0,1208
; CHECK-NEXT: llgtr 1,0
@@ -261,7 +261,7 @@ entry:
define void @test_misc_5(ptr %f) {
entry:
-; CHECK-LABEL: test_misc_5:
+; CHECK-LABEL: test_misc_5 DS 0H
; CHECK: l 0,548
; CHECK-NEXT: lg 6,8(5)
; CHECK-NEXT: lg 5,0(5)
@@ -277,7 +277,7 @@ entry:
define signext i32 @get_processor_count() {
entry:
-; CHECK-LABEL: get_processor_count:
+; CHECK-LABEL: get_processor_count DS 0H
; CHECK: lhi 0,660
; CHECK-NEXT: a 0,16
; CHECK-NEXT: llgtr 1,0
@@ -296,7 +296,7 @@ entry:
define void @spill_ptr32_args_to_registers(i8 addrspace(1)* %p) {
entry:
-; CHECK-LABEL: spill_ptr32_args_to_registers:
+; CHECK-LABEL: spill_ptr32_args_to_registers DS 0H
; CHECK: stmg 6,7,1872(4)
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: lgr 2,1
@@ -327,7 +327,7 @@ declare void @g(i32 signext, ...)
; cast to __ptr32, setting the upper 32 bit to zero.
;
define signext i32 @setlength() {
-; CHECK-LABEL: setlength:
+; CHECK-LABEL: setlength DS 0H
; CHECK: basr 7,6
; CHECK: lgr [[MALLOC:[0-9]+]],3
; CHECK: basr 7,6
@@ -351,7 +351,7 @@ entry:
; the function now returns a __ptr32.
;
define signext i32 @setlength2() {
-; CHECK-LABEL: setlength2:
+; CHECK-LABEL: setlength2 DS 0H
; CHECK: basr 7,6
; CHECK: lgr [[MALLOC:[0-9]+]],3
; CHECK: basr 7,6
diff --git a/llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll b/llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll
index 616cb370f6fc8..f3bdf64683bb6 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll
@@ -2,7 +2,7 @@
;
; RUN: llc < %s -mtriple=s390x-ibm-zos | FileCheck %s
-; CHECK-LABEL: DoIt:
+; CHECK-LABEL: DoIt DS 0H
; CHECK: stmg 6,7,1840(4)
; CHECK: aghi 4,-224
; CHECK: lg 1,0(5)
@@ -25,7 +25,7 @@ entry:
declare void @DoFunc()
declare void @Caller(ptr noundef)
-; CHECK-LABEL: get_i:
+; CHECK-LABEL: get_i DS 0H
; CHECK: stmg 6,8,1872(4)
; CHECK: aghi 4,-192
; CHECK: lg 1,24(5)
@@ -56,14 +56,18 @@ entry:
declare signext i32 @callout(i32 signext)
; CHECK: stdin#C CSECT
-; CHECK: C_WSA64 CATTR ALIGN(4),FILL(0),DEFLOAD,NOTEXECUTABLE,RMODE(64),PART(stdin#S)
+; CHECK: C_WSA64 CATTR ALIGN(4),FILL(0),DEFLOAD,NOTEXECUTABLE,RMODE(64),PART(stdi
+; CHECK: in#S)
; CHECK: stdin#S XATTR LINKAGE(XPLINK),REFERENCE(DATA),SCOPE(SECTION)
-; CHECK: .set L#DoFunc at indirect0, DoFunc
-; CHECK: .indirect_symbol L#DoFunc at indirect0
-; CHECK: .quad VD(L#DoFunc at indirect0) * Offset 0 pointer to function descriptor DoFunc
-; CHECK: .quad RD(Caller) * Offset 8 function descriptor of Caller
-; CHECK: .quad VD(Caller)
-; CHECK: .quad AD(i2) * Offset 24 pointer to data symbol i2
-; CHECK: .quad AD(i) * Offset 32 pointer to data symbol i
-; CHECK: .quad RD(callout) * Offset 40 function descriptor of callout
-; CHECK: .quad VD(callout)
+; CHECK: * Offset 0 pointer to function descriptor DoFunc
+; CHECK: DC VD(L#DoFunc at indirect0)
+; CHECK: * Offset 8 function descriptor of Caller
+; CHECK: DC RD(Caller)
+; CHECK: DC VD(Caller)
+; CHECK: * Offset 24 pointer to data symbol i2
+; CHECK: DC AD(i2)
+; CHECK: * Offset 32 pointer to data symbol i
+; CHECK: DC AD(i)
+; CHECK: * Offset 40 function descriptor of callout
+; CHECK: DC RD(callout)
+; CHECK: DC VD(callout)
diff --git a/llvm/test/CodeGen/SystemZ/zos-ada.ll b/llvm/test/CodeGen/SystemZ/zos-ada.ll
index 8f00f32c1b805..dcdcf2d6c6dc8 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ada.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ada.ll
@@ -2,7 +2,7 @@
;
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
-; CHECK-LABEL: caller:
+; CHECK-LABEL: caller DS 0H
; CHECK: stmg 6,8,1872(4)
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: lgr 8,5
diff --git a/llvm/test/CodeGen/SystemZ/zos-alias-unsupported.ll b/llvm/test/CodeGen/SystemZ/zos-alias-unsupported.ll
index 1a01e91d1f8f2..5aeebcd157c84 100644
--- a/llvm/test/CodeGen/SystemZ/zos-alias-unsupported.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-alias-unsupported.ll
@@ -1,6 +1,6 @@
; Test aliasing errors on z/OS
-; RUN: not llc < %s -mtriple=s390x-ibm-zos -emit-gnuas-syntax-on-zos=0 2>&1 | FileCheck %s
+; RUN: not llc < %s -mtriple=s390x-ibm-zos 2>&1 | FileCheck %s
; CHECK: error: Only aliases to functions is supported in GOFF.
; CHECK: error: Weak alias/reference not supported on z/OS
diff --git a/llvm/test/CodeGen/SystemZ/zos-dwarf.ll b/llvm/test/CodeGen/SystemZ/zos-dwarf.ll
index 919602c799f7a..372126f5d5737 100644
--- a/llvm/test/CodeGen/SystemZ/zos-dwarf.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-dwarf.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=s390x-ibm-zos -emit-gnuas-syntax-on-zos=0 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-ibm-zos | FileCheck %s
@fortytwo = hidden global i32 42, align 4,...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/181222
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