[llvm] [AMDGPU] Fix handling of setting register classes in MFMA scheduler rewrite stage (PR #181047)

[Tony Linthicum via llvm-commits]

================
@@ -0,0 +1,1867 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -O1 -amdgpu-disable-rewrite-mfma-form-sched-stage=false -verify-machineinstrs < %s
+
+target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
----------------
tlinthic wrote:

I don't see how it can reasonably be made smaller and I'm not sure what making it a MIR test would do to help.  It needs to be large enough to force the rewrite stage to attempt to rewrite it and also have a cost profile that makes it reject the rewrite.  Now, it's entirely possible that you could hand write a test case that is smaller, but it would take some time and it really doesn't strike me as necessary.  That said, if you and Matt insist then, of course, I'll do it.

https://github.com/llvm/llvm-project/pull/181047