[llvm] [AMDGPU] Fix handling of setting register classes in MFMA scheduler rewrite stage (PR #181047)

[Shilei Tian via llvm-commits]

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@@ -0,0 +1,1867 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -O1 -amdgpu-disable-rewrite-mfma-form-sched-stage=false -verify-machineinstrs < %s
+
+target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
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shiltian wrote:

Use named variables is our general rule for IR test cases and we pointed that out every time we see unnamed variables. CC @arsenm 

I wonder if we can get further smaller. If this is for scheduler, maybe a MIR test instead of an IR one?

https://github.com/llvm/llvm-project/pull/181047