[llvm] [NFC] Pre-Commit test case for __builtin_ppc_test_data_class (PR #181181)

[zhijian lin via llvm-commits]

https://github.com/diggerlin created https://github.com/llvm/llvm-project/pull/181181

add a pre-commit test case for __builtin_ppc_test_data_class

>From 3e7fa42906636b0857d11a68249a1e6ffde6350b Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Thu, 12 Feb 2026 11:45:12 -0500
Subject: [PATCH] add precommit test case for __builtin_ppc_test_data_class

---
 .../CodeGen/PowerPC/ppc_test_data_class.ll    | 77 +++++++++++++++++++
 1 file changed, 77 insertions(+)
 create mode 100644 llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll

diff --git a/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll b/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
new file mode 100644
index 0000000000000..7e9e7bece3f1f
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/ppc_test_data_class.ll
@@ -0,0 +1,77 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc   -mtriple=powerpc-ibm-aix7.2.0.0  -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck --check-prefix=AIX-PWR9 %s
+; RUN: llc   -mtriple=powerpc-ibm-aix7.2.0.0  -verify-machineinstrs -mcpu=pwr10 < %s | FileCheck --check-prefix=AIX-PWR10 %s
+; RUN: llc   -mtriple=powerpc-ibm64-aix7.2.0.0  -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck --check-prefix=AIX-PWR9 %s
+; RUN: llc   -mtriple=powerpc-ibm64-aix7.2.0.0  -verify-machineinstrs -mcpu=pwr10 < %s | FileCheck --check-prefix=AIX-PWR10 %s
+; RUN: llc   -mtriple=powerpc64le-unknown-unknown  -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck --check-prefix=LNXLE64-PWR9 %s
+; RUN: llc   -mtriple=powerpc64le-unknown-unknown  -verify-machineinstrs -mcpu=pwr10 < %s | FileCheck --check-prefix=LNXLE64-PWR10 %s
+; RUN: llc   -mtriple=powerpcle-unknown-unknown  -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck --check-prefix=LNXLE-PWR9 %s
+; RUN: llc   -mtriple=powerpcle-unknown-unknown  -verify-machineinstrs -mcpu=pwr10 < %s | FileCheck --check-prefix=LNXLE-PWR10 %s
+define noundef zeroext i1 @_Z16ossIsValidDoubled(double noundef %in) local_unnamed_addr  {
+; AIX-PWR9-LABEL: _Z16ossIsValidDoubled:
+; AIX-PWR9:       # %bb.0: # %entry
+; AIX-PWR9-NEXT:    xststdcdp 0, 1, 115
+; AIX-PWR9-NEXT:    li 3, 0
+; AIX-PWR9-NEXT:    li 4, 1
+; AIX-PWR9-NEXT:    iseleq 3, 4, 3
+; AIX-PWR9-NEXT:    cntlzw 3, 3
+; AIX-PWR9-NEXT:    rlwinm 3, 3, 27, 31, 31
+; AIX-PWR9-NEXT:    blr
+;
+; AIX-PWR10-LABEL: _Z16ossIsValidDoubled:
+; AIX-PWR10:       # %bb.0: # %entry
+; AIX-PWR10-NEXT:    xststdcdp 0, 1, 115
+; AIX-PWR10-NEXT:    li 3, 0
+; AIX-PWR10-NEXT:    li 4, 1
+; AIX-PWR10-NEXT:    iseleq 3, 4, 3
+; AIX-PWR10-NEXT:    cntlzw 3, 3
+; AIX-PWR10-NEXT:    rlwinm 3, 3, 27, 31, 31
+; AIX-PWR10-NEXT:    blr
+;
+; LNXLE64-PWR9-LABEL: _Z16ossIsValidDoubled:
+; LNXLE64-PWR9:       # %bb.0: # %entry
+; LNXLE64-PWR9-NEXT:    xststdcdp 0, 1, 115
+; LNXLE64-PWR9-NEXT:    li 3, 0
+; LNXLE64-PWR9-NEXT:    li 4, 1
+; LNXLE64-PWR9-NEXT:    iseleq 3, 4, 3
+; LNXLE64-PWR9-NEXT:    cntlzw 3, 3
+; LNXLE64-PWR9-NEXT:    srwi 3, 3, 5
+; LNXLE64-PWR9-NEXT:    blr
+;
+; LNXLE64-PWR10-LABEL: _Z16ossIsValidDoubled:
+; LNXLE64-PWR10:       # %bb.0: # %entry
+; LNXLE64-PWR10-NEXT:    xststdcdp 0, 1, 115
+; LNXLE64-PWR10-NEXT:    li 3, 0
+; LNXLE64-PWR10-NEXT:    li 4, 1
+; LNXLE64-PWR10-NEXT:    iseleq 3, 4, 3
+; LNXLE64-PWR10-NEXT:    cntlzw 3, 3
+; LNXLE64-PWR10-NEXT:    rlwinm 3, 3, 27, 31, 31
+; LNXLE64-PWR10-NEXT:    blr
+;
+; LNXLE-PWR9-LABEL: _Z16ossIsValidDoubled:
+; LNXLE-PWR9:       # %bb.0: # %entry
+; LNXLE-PWR9-NEXT:    xststdcdp 0, 1, 115
+; LNXLE-PWR9-NEXT:    li 3, 0
+; LNXLE-PWR9-NEXT:    li 4, 1
+; LNXLE-PWR9-NEXT:    iseleq 3, 4, 3
+; LNXLE-PWR9-NEXT:    cntlzw 3, 3
+; LNXLE-PWR9-NEXT:    rlwinm 3, 3, 27, 31, 31
+; LNXLE-PWR9-NEXT:    blr
+;
+; LNXLE-PWR10-LABEL: _Z16ossIsValidDoubled:
+; LNXLE-PWR10:       # %bb.0: # %entry
+; LNXLE-PWR10-NEXT:    xststdcdp 0, 1, 115
+; LNXLE-PWR10-NEXT:    li 3, 0
+; LNXLE-PWR10-NEXT:    li 4, 1
+; LNXLE-PWR10-NEXT:    iseleq 3, 4, 3
+; LNXLE-PWR10-NEXT:    cntlzw 3, 3
+; LNXLE-PWR10-NEXT:    rlwinm 3, 3, 27, 31, 31
+; LNXLE-PWR10-NEXT:    blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f64(double %in, i32 115)
+  %tobool.not = icmp eq i32 %test_data_class, 0
+  ret i1 %tobool.not
+}
+
+declare i32 @llvm.ppc.test.data.class.f64(double, i32 immarg)
+