[llvm] [UTC][VPlan] Use `-vplan-print-after` for VPlan-dump-based tests (PR #178736)
Andrei Elovikov via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 12 08:09:58 PST 2026
https://github.com/eas updated https://github.com/llvm/llvm-project/pull/178736
>From 3cc13ab6ee4ab5397d343d4b69c0ce74e8d11e60 Mon Sep 17 00:00:00 2001
From: Andrei Elovikov <andrei.elovikov at sifive.com>
Date: Tue, 27 Jan 2026 16:59:55 -0800
Subject: [PATCH 1/5] [VPlan] Print function name in `-vplan-print-after*`
---
.../Transforms/Vectorize/VPlanTransforms.h | 6 +-
.../LoopVectorize/vplan-print-after-all.ll | 78 +++++++++----------
.../LoopVectorize/vplan-print-after.ll | 8 +-
3 files changed, 48 insertions(+), 44 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.h b/llvm/lib/Transforms/Vectorize/VPlanTransforms.h
index 07ad08aef471f..c4dcf740d6b07 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.h
@@ -59,7 +59,11 @@ struct VPlanTransforms {
any_of(VPlanPrintAfterPasses, [PassName](StringRef Entry) {
return Regex(Entry).match(PassName);
}))) {
- dbgs() << "VPlan after " << PassName << '\n';
+
+ dbgs()
+ << "VPlan for loop in '"
+ << Plan.getScalarHeader()->getIRBasicBlock()->getParent()->getName()
+ << "' after " << PassName << '\n';
dbgs() << Plan << '\n';
}
#endif
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-print-after-all.ll b/llvm/test/Transforms/LoopVectorize/vplan-print-after-all.ll
index 5b68887f0f7da..ae09cb1b1002e 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-print-after-all.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-print-after-all.ll
@@ -1,55 +1,55 @@
-; RUN: opt -passes=loop-vectorize -disable-output -vplan-print-after-all -force-vector-width=4 -vplan-verify-each < %s 2>&1 | FileCheck %s --implicit-check-not "VPlan after"
+; RUN: opt -passes=loop-vectorize -disable-output -vplan-print-after-all -force-vector-width=4 -vplan-verify-each < %s 2>&1 | FileCheck %s --implicit-check-not "VPlan for loop in 'foo' after"
; RUN: opt -passes=loop-vectorize -disable-output -vplan-print-after-all -force-vector-width=4 -vplan-verify-each < %s 2>&1 | FileCheck %s --check-prefix CHECK-DUMP
; REQUIRES: asserts
; Verify that `-vplan-print-after-all` option works.
-; CHECK: VPlan after printAfterInitialConstruction
-; CHECK: VPlan after VPlanTransforms::clearReductionWrapFlags
-; CHECK: VPlan after VPlanTransforms::optimizeFindIVReductions
-; CHECK: VPlan after VPlanTransforms::handleMultiUseReductions
-; CHECK: VPlan after VPlanTransforms::handleMaxMinNumReductions
-; CHECK: VPlan after VPlanTransforms::handleFindLastReductions
-; CHECK: VPlan after VPlanTransforms::createPartialReductions
-; CHECK: VPlan after VPlanTransforms::convertToAbstractRecipes
-; CHECK: VPlan after VPlanTransforms::createInterleaveGroups
-; CHECK: VPlan after VPlanTransforms::replaceSymbolicStrides
-; CHECK: VPlan after VPlanTransforms::dropPoisonGeneratingRecipes
-; CHECK: VPlan after VPlanTransforms::adjustFixedOrderRecurrences
-; CHECK: VPlan after VPlanTransforms::truncateToMinimalBitwidths
-; CHECK: VPlan after removeRedundantCanonicalIVs
-; CHECK: VPlan after removeRedundantInductionCasts
-; CHECK: VPlan after simplifyRecipes
-; CHECK: VPlan after removeDeadRecipes
-; CHECK: VPlan after simplifyBlends
-; CHECK: VPlan after legalizeAndOptimizeInductions
-; CHECK: VPlan after narrowToSingleScalarRecipes
-; CHECK: VPlan after removeRedundantExpandSCEVRecipes
-; CHECK: VPlan after simplifyRecipes
-; CHECK: VPlan after removeBranchOnConst
-; CHECK: VPlan after removeDeadRecipes
-; CHECK: VPlan after createAndOptimizeReplicateRegions
-; CHECK: VPlan after hoistInvariantLoads
-; CHECK: VPlan after mergeBlocksIntoPredecessors
-; CHECK: VPlan after licm
-; CHECK: VPlan after VPlanTransforms::optimize
-; CHECK: VPlan after VPlanTransforms::materializeConstantVectorTripCount
-; CHECK: VPlan after VPlanTransforms::unrollByUF
-; CHECK: VPlan after VPlanTransforms::materializePacksAndUnpacks
-; CHECK: VPlan after VPlanTransforms::materializeBroadcasts
-; CHECK: VPlan after VPlanTransforms::replicateByVF
-; CHECK: VPlan after printFinalVPlan
+; CHECK: VPlan for loop in 'foo' after printAfterInitialConstruction
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::clearReductionWrapFlags
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::optimizeFindIVReductions
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::handleMultiUseReductions
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::handleMaxMinNumReductions
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::handleFindLastReductions
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::createPartialReductions
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::convertToAbstractRecipes
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::createInterleaveGroups
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::replaceSymbolicStrides
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::dropPoisonGeneratingRecipes
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::adjustFixedOrderRecurrences
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::truncateToMinimalBitwidths
+; CHECK: VPlan for loop in 'foo' after removeRedundantCanonicalIVs
+; CHECK: VPlan for loop in 'foo' after removeRedundantInductionCasts
+; CHECK: VPlan for loop in 'foo' after simplifyRecipes
+; CHECK: VPlan for loop in 'foo' after removeDeadRecipes
+; CHECK: VPlan for loop in 'foo' after simplifyBlends
+; CHECK: VPlan for loop in 'foo' after legalizeAndOptimizeInductions
+; CHECK: VPlan for loop in 'foo' after narrowToSingleScalarRecipes
+; CHECK: VPlan for loop in 'foo' after removeRedundantExpandSCEVRecipes
+; CHECK: VPlan for loop in 'foo' after simplifyRecipes
+; CHECK: VPlan for loop in 'foo' after removeBranchOnConst
+; CHECK: VPlan for loop in 'foo' after removeDeadRecipes
+; CHECK: VPlan for loop in 'foo' after createAndOptimizeReplicateRegions
+; CHECK: VPlan for loop in 'foo' after hoistInvariantLoads
+; CHECK: VPlan for loop in 'foo' after mergeBlocksIntoPredecessors
+; CHECK: VPlan for loop in 'foo' after licm
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::optimize
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::materializeConstantVectorTripCount
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::unrollByUF
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::materializePacksAndUnpacks
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::materializeBroadcasts
+; CHECK: VPlan for loop in 'foo' after VPlanTransforms::replicateByVF
+; CHECK: VPlan for loop in 'foo' after printFinalVPlan
; Also verify that VPlans are actually printed (we aren't interested in the
; exact dump content, just that it's performed):
-; CHECK-DUMP: VPlan after printAfterInitialConstruction
+; CHECK-DUMP: VPlan for loop in 'foo' after printAfterInitialConstruction
; CHECK-DUMP-NEXT: VPlan ' for UF>=1' {
;
-; CHECK-DUMP: VPlan after VPlanTransforms::optimize{{$}}
+; CHECK-DUMP: VPlan for loop in 'foo' after VPlanTransforms::optimize{{$}}
; CHECK-DUMP-NEXT: VPlan 'Initial VPlan for VF={4},UF>=1' {
;
-; CHECK-DUMP: VPlan after printFinalVPlan
+; CHECK-DUMP: VPlan for loop in 'foo' after printFinalVPlan
; CHECK-DUMP-NEXT: VPlan 'Final VPlan for VF={4},UF={1}' {
define void @foo(ptr %ptr, i64 %n) {
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-print-after.ll b/llvm/test/Transforms/LoopVectorize/vplan-print-after.ll
index 8014a4e480d65..56a2ad83007a8 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-print-after.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-print-after.ll
@@ -3,13 +3,13 @@
; RUN: 2>&1 | FileCheck %s --implicit-check-not "VPlan after"
; REQUIRES: asserts
-; CHECK: VPlan after simplifyRecipes
+; CHECK: VPlan for loop in 'foo' after simplifyRecipes
; CHECK-NEXT: VPlan 'Initial VPlan for VF={4},UF>=1' {
-; CHECK: VPlan after simplifyBlends
+; CHECK: VPlan for loop in 'foo' after simplifyBlends
; CHECK-NEXT: VPlan 'Initial VPlan for VF={4},UF>=1' {
-; CHECK: VPlan after simplifyRecipes
+; CHECK: VPlan for loop in 'foo' after simplifyRecipes
; CHECK-NEXT: VPlan 'Initial VPlan for VF={4},UF>=1' {
-; CHECK: VPlan after printFinalVPlan
+; CHECK: VPlan for loop in 'foo' after printFinalVPlan
; CHECK-NEXT: VPlan 'Final VPlan for VF={4},UF={1}' {
define void @foo(ptr %ptr, i64 %n) {
>From e46f57bf5f7ddab430b7b871ce1573f4ab184d9d Mon Sep 17 00:00:00 2001
From: Andrei Elovikov <andrei.elovikov at sifive.com>
Date: Fri, 6 Feb 2026 12:20:43 -0800
Subject: [PATCH 2/5] Update VPlan UTC to use `-vplan-print-after=`
---
.../first-order-recurrence-chains-vplan.ll | 2 +-
...-order-recurrence-sink-replicate-region.ll | 2 +-
.../LoopVectorize/vplan-printing-metadata.ll | 2 +-
.../vplan-printing-reductions.ll | 2 +-
.../LoopVectorize/vplan-printing.ll | 2 +-
.../vplan-sink-scalars-and-merge-vf1.ll | 2 +-
.../Inputs/vplan.ll | 4 +-
.../Inputs/vplan.ll.expected | 4 +-
llvm/utils/UpdateTestChecks/common.py | 4 ++
llvm/utils/update_analyze_test_checks.py | 44 +++----------------
10 files changed, 20 insertions(+), 48 deletions(-)
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
index 9ab2557387877..648ea5297f042 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
+++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
; REQUIRES: asserts
-; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -debug-only=loop-vectorize -disable-output -S %s 2>&1 | FileCheck %s
+; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -vplan-print-after="optimize$" -disable-output -S %s 2>&1 | FileCheck %s
define void @test_chained_first_order_recurrences_1(ptr %ptr) {
; CHECK-LABEL: 'test_chained_first_order_recurrences_1'
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
index 6992a441f9444..b398a96662f47 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
+++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
; REQUIRES: asserts
-; RUN: opt < %s -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -force-widen-divrem-via-safe-divisor=0 -disable-output -debug-only=loop-vectorize 2>&1 | FileCheck %s
+; RUN: opt < %s -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -force-widen-divrem-via-safe-divisor=0 -disable-output -vplan-print-after="optimize$" 2>&1 | FileCheck %s
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll
index 027bfe859c828..d780a799c9d49 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
; REQUIRES: asserts
-; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -disable-output %s 2>&1 | FileCheck %s
+; RUN: opt -passes=loop-vectorize -vplan-print-after="optimize$" -force-vector-interleave=1 -force-vector-width=4 -disable-output %s 2>&1 | FileCheck %s
define void @test_widen_metadata(ptr noalias %A, ptr noalias %B, i32 %n) {
; CHECK-LABEL: 'test_widen_metadata'
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
index b282a9079c996..46f6e872ab2e9 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
; REQUIRES: asserts
-; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -disable-output %s 2>&1 | FileCheck %s
+; RUN: opt -passes=loop-vectorize -vplan-print-after="optimize$" -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -disable-output %s 2>&1 | FileCheck %s
; Tests for printing VPlans with reductions.
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
index 1d5d71b0a64c0..c9a186cb3f1f8 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
; REQUIRES: asserts
-; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -enable-interleaved-mem-accesses=true -enable-masked-interleaved-mem-accesses -force-widen-divrem-via-safe-divisor=0 -disable-output %s 2>&1 | FileCheck --strict-whitespace %s
+; RUN: opt -passes=loop-vectorize -vplan-print-after="optimize$" -force-vector-interleave=1 -force-vector-width=4 -enable-interleaved-mem-accesses=true -enable-masked-interleaved-mem-accesses -force-widen-divrem-via-safe-divisor=0 -disable-output %s 2>&1 | FileCheck --strict-whitespace %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll b/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll
index 3896e67c81b1b..63c2d618bbd26 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
; REQUIRES: asserts
-; RUN: opt -passes=loop-vectorize -force-vector-interleave=2 -force-vector-width=1 -debug -disable-output %s 2>&1 | FileCheck %s
+; RUN: opt -passes=loop-vectorize -force-vector-interleave=2 -force-vector-width=1 -vplan-print-after="optimize$" -disable-output %s 2>&1 | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
diff --git a/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll b/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll
index 1ef134466cfcf..8b0dd716fc1ff 100644
--- a/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll
+++ b/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll
@@ -1,5 +1,5 @@
-; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-width=4 \
-; RUN: -disable-output %s 2>&1 | FileCheck %s
+; RUN: opt -passes=loop-vectorize -vplan-print-after="optimize$" \
+; RUN: -force-vector-width=4 -disable-output %s 2>&1 | FileCheck %s
define void @simple(ptr %p, i64 %n) {
entry:
diff --git a/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll.expected b/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll.expected
index 5d0cf220faf75..970ba6afb567d 100644
--- a/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll.expected
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
-; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-width=4 \
-; RUN: -disable-output %s 2>&1 | FileCheck %s
+; RUN: opt -passes=loop-vectorize -vplan-print-after="optimize$" \
+; RUN: -force-vector-width=4 -disable-output %s 2>&1 | FileCheck %s
define void @simple(ptr %p, i64 %n) {
; CHECK-LABEL: 'simple'
diff --git a/llvm/utils/UpdateTestChecks/common.py b/llvm/utils/UpdateTestChecks/common.py
index 9cca0a7ad5d38..5fcc056a4bb6d 100644
--- a/llvm/utils/UpdateTestChecks/common.py
+++ b/llvm/utils/UpdateTestChecks/common.py
@@ -597,6 +597,10 @@ def invoke_tool(exe, cmd_args, ir, preprocess_cmd=None, verbose=False):
r"^\s*\'(?P<func>[\w.$-]+?)\'[^\n]*" r"\s*\n(?P<body>.*)$", flags=(re.X | re.S)
)
+VPLAN_RE = re.compile(
+ r"\'(?P<func>[\w.$-]+?)\'[^\n]*\n(?P<body>.*)\n$", flags=(re.X | re.S)
+)
+
IR_FUNCTION_RE = re.compile(r'^\s*define\s+(?:internal\s+)?[^@]*@"?([\w.$-]+)"?\s*\(')
IR_FUNCTION_LABEL_RE = re.compile(
r'^\s*(?:define\s+(?:internal\s+)?[^@]*)?@"?([\w.$-]+)"?\s*\('
diff --git a/llvm/utils/update_analyze_test_checks.py b/llvm/utils/update_analyze_test_checks.py
index bd249a53f458f..cc55f72425b16 100755
--- a/llvm/utils/update_analyze_test_checks.py
+++ b/llvm/utils/update_analyze_test_checks.py
@@ -41,27 +41,6 @@
from UpdateTestChecks import common
-def extract_vplan(raw_output):
- """
- Extract a VPlan block from loop-vectorize debug output using brace-depth
- tracking.
- TODO: Remove once only -vplan-print-after is supported.
- """
- result = []
- brace_depth = 0
- for line in raw_output.splitlines():
- if not brace_depth and line.startswith("VPlan 'Initial VPlan"):
- brace_depth = 1
- result.append(line)
- continue
- if brace_depth:
- brace_depth += line.count("{") - line.count("}")
- result.append(line)
- if brace_depth == 0:
- break
- return "\n".join(result) if result else None
-
-
def update_test(opt_basename: str, ti: common.TestInfo):
triple_in_ir = None
for l in ti.input_lines:
@@ -120,33 +99,22 @@ def update_test(opt_basename: str, ti: common.TestInfo):
raw_tool_outputs = common.invoke_tool(ti.args.opt_binary, opt_args, ti.path)
- # Detect VPlan output for LV pass. Don't use VPlan mode if filters are
- # active since the user is likely filtering to specific LV debug lines
- # (e.g., cost model).
- is_vplan_output = (
- not ti.args.filters
- and re.search(r"VPlan 'Initial VPlan", raw_tool_outputs) is not None
- )
-
regex_map = {
r"Printing analysis ": common.ANALYZE_FUNCTION_RE,
r"(LV|LDist|HashRecognize): Checking a loop in ": common.LOOP_PASS_DEBUG_RE,
+ r"VPlan for loop in ": common.VPLAN_RE,
}
for split_by, regex in regex_map.items():
if re.search(split_by, raw_tool_outputs) is None:
continue
for raw_tool_output in re.split(split_by, raw_tool_outputs):
- if is_vplan_output:
- vplan_output = extract_vplan(raw_tool_output)
- if not vplan_output:
- continue
- # Reconstruct minimal output: function header line + VPlan
- func_header = raw_tool_output.split("\n")[0]
- raw_tool_output = "\n".join([func_header, vplan_output])
-
# For VPlan mode, don't scrub whitespace - preserve exact alignment
- scrubber = (lambda body: body) if is_vplan_output else common.scrub_body
+ scrubber = (
+ (lambda body: body)
+ if regex == common.VPLAN_RE
+ else common.scrub_body
+ )
builder.process_run_line(
regex,
scrubber,
>From 21275e9b41f28ee1b8988c11bd7e64f5af94b4f7 Mon Sep 17 00:00:00 2001
From: Andrei Elovikov <andrei.elovikov at sifive.com>
Date: Wed, 11 Feb 2026 08:01:55 -0800
Subject: [PATCH 3/5] Remove spurious newline
---
llvm/lib/Transforms/Vectorize/VPlanTransforms.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.h b/llvm/lib/Transforms/Vectorize/VPlanTransforms.h
index c4dcf740d6b07..edf21115e2bab 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.h
@@ -59,7 +59,6 @@ struct VPlanTransforms {
any_of(VPlanPrintAfterPasses, [PassName](StringRef Entry) {
return Regex(Entry).match(PassName);
}))) {
-
dbgs()
<< "VPlan for loop in '"
<< Plan.getScalarHeader()->getIRBasicBlock()->getParent()->getName()
>From 752fedb9303a12be74e3f71493b181fafca14bac Mon Sep 17 00:00:00 2001
From: Andrei Elovikov <andrei.elovikov at sifive.com>
Date: Wed, 11 Feb 2026 08:19:51 -0800
Subject: [PATCH 4/5] Extend `CHECK-LABEL` line
---
.../first-order-recurrence-chains-vplan.ll | 8 ++--
...-order-recurrence-sink-replicate-region.ll | 12 +++---
.../LoopVectorize/vplan-printing-metadata.ll | 6 +--
.../vplan-printing-reductions.ll | 38 +++++++++----------
.../LoopVectorize/vplan-printing.ll | 28 +++++++-------
.../vplan-sink-scalars-and-merge-vf1.ll | 2 +-
.../Inputs/vplan.ll.expected | 2 +-
llvm/utils/UpdateTestChecks/common.py | 3 +-
llvm/utils/update_analyze_test_checks.py | 3 ++
9 files changed, 53 insertions(+), 49 deletions(-)
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
index 648ea5297f042..1b11922c2b6ce 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
+++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
@@ -4,7 +4,7 @@
; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -vplan-print-after="optimize$" -disable-output -S %s 2>&1 | FileCheck %s
define void @test_chained_first_order_recurrences_1(ptr %ptr) {
-; CHECK-LABEL: 'test_chained_first_order_recurrences_1'
+; CHECK-LABEL: VPlan for loop in 'test_chained_first_order_recurrences_1'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -88,7 +88,7 @@ exit:
}
define void @test_chained_first_order_recurrences_3(ptr %ptr) {
-; CHECK-LABEL: 'test_chained_first_order_recurrences_3'
+; CHECK-LABEL: VPlan for loop in 'test_chained_first_order_recurrences_3'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -186,7 +186,7 @@ exit:
; Sinking would require moving a recipe with side effects (store). Instead,
; for.x.next can be hoisted.
define i32 @test_chained_first_order_recurrences_4(ptr %base, i64 %x) {
-; CHECK-LABEL: 'test_chained_first_order_recurrences_4'
+; CHECK-LABEL: VPlan for loop in 'test_chained_first_order_recurrences_4'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -272,7 +272,7 @@ ret:
}
define i32 @test_chained_first_order_recurrences_5_hoist_to_load(ptr %base) {
-; CHECK-LABEL: 'test_chained_first_order_recurrences_5_hoist_to_load'
+; CHECK-LABEL: VPlan for loop in 'test_chained_first_order_recurrences_5_hoist_to_load'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
index b398a96662f47..d50ffe151d84e 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
+++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
@@ -8,7 +8,7 @@ target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
; first-order recurrence.
define void @sink_replicate_region_1(i32 %x, ptr %ptr, ptr noalias %dst) optsize {
-; CHECK-LABEL: 'sink_replicate_region_1'
+; CHECK-LABEL: VPlan for loop in 'sink_replicate_region_1'
; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -124,7 +124,7 @@ exit:
}
define void @sink_replicate_region_2(i32 %x, i8 %y, ptr %ptr, i32 %z) optsize {
-; CHECK-LABEL: 'sink_replicate_region_2'
+; CHECK-LABEL: VPlan for loop in 'sink_replicate_region_2'
; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -221,7 +221,7 @@ exit:
}
define i32 @sink_replicate_region_3_reduction(i32 %x, i8 %y, ptr %ptr) optsize {
-; CHECK-LABEL: 'sink_replicate_region_3_reduction'
+; CHECK-LABEL: VPlan for loop in 'sink_replicate_region_3_reduction'
; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF * UF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = vector-trip-count
@@ -321,7 +321,7 @@ exit:
; To sink the replicate region containing %rem, we need to split the block
; containing %conv at the end, because %conv is the last recipe in the block.
define void @sink_replicate_region_4_requires_split_at_end_of_block(i32 %x, ptr %ptr, ptr noalias %dst) optsize {
-; CHECK-LABEL: 'sink_replicate_region_4_requires_split_at_end_of_block'
+; CHECK-LABEL: VPlan for loop in 'sink_replicate_region_4_requires_split_at_end_of_block'
; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -465,7 +465,7 @@ exit:
; Test case that requires sinking a recipe in a replicate region after another replicate region.
define void @sink_replicate_region_after_replicate_region(ptr %ptr, ptr noalias %dst.2, i32 %x, i8 %y) optsize {
-; CHECK-LABEL: 'sink_replicate_region_after_replicate_region'
+; CHECK-LABEL: VPlan for loop in 'sink_replicate_region_after_replicate_region'
; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -565,7 +565,7 @@ exit: ; preds = %loop
}
define void @need_new_block_after_sinking_pr56146(i32 %x, ptr %src, ptr noalias %dst) {
-; CHECK-LABEL: 'need_new_block_after_sinking_pr56146'
+; CHECK-LABEL: VPlan for loop in 'need_new_block_after_sinking_pr56146'
; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll
index d780a799c9d49..1571a85129a3d 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll
@@ -4,7 +4,7 @@
; RUN: opt -passes=loop-vectorize -vplan-print-after="optimize$" -force-vector-interleave=1 -force-vector-width=4 -disable-output %s 2>&1 | FileCheck %s
define void @test_widen_metadata(ptr noalias %A, ptr noalias %B, i32 %n) {
-; CHECK-LABEL: 'test_widen_metadata'
+; CHECK-LABEL: VPlan for loop in 'test_widen_metadata'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -85,7 +85,7 @@ exit:
declare float @llvm.sqrt.f32(float)
define void @test_intrinsic_with_metadata(ptr noalias %A, ptr noalias %B, i32 %n) {
-; CHECK-LABEL: 'test_intrinsic_with_metadata'
+; CHECK-LABEL: VPlan for loop in 'test_intrinsic_with_metadata'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -158,7 +158,7 @@ exit:
}
define void @test_widen_with_multiple_metadata(ptr noalias %A, ptr noalias %B, i32 %n) {
-; CHECK-LABEL: 'test_widen_with_multiple_metadata'
+; CHECK-LABEL: VPlan for loop in 'test_widen_with_multiple_metadata'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
index 46f6e872ab2e9..ae1705f48520a 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
@@ -6,7 +6,7 @@
; Tests for printing VPlans with reductions.
define float @print_reduction(i64 %n, ptr noalias %y) {
-; CHECK-LABEL: 'print_reduction'
+; CHECK-LABEL: VPlan for loop in 'print_reduction'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -79,7 +79,7 @@ exit: ; preds = %loop, %entry
}
define void @print_reduction_with_invariant_store(i64 %n, ptr noalias %y, ptr noalias %dst) {
-; CHECK-LABEL: 'print_reduction_with_invariant_store'
+; CHECK-LABEL: VPlan for loop in 'print_reduction_with_invariant_store'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -154,7 +154,7 @@ exit: ; preds = %loop, %entry
}
define float @print_fmuladd_strict(ptr %a, ptr %b, i64 %n) {
-; CHECK-LABEL: 'print_fmuladd_strict'
+; CHECK-LABEL: VPlan for loop in 'print_fmuladd_strict'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -236,7 +236,7 @@ exit:
}
define i64 @find_last_iv(ptr %a, i64 %n, i64 %start) {
-; CHECK-LABEL: 'find_last_iv'
+; CHECK-LABEL: VPlan for loop in 'find_last_iv'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -314,7 +314,7 @@ exit:
}
define i64 @print_extended_reduction(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) {
-; CHECK-LABEL: 'print_extended_reduction'
+; CHECK-LABEL: VPlan for loop in 'print_extended_reduction'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -390,7 +390,7 @@ exit:
}
define i64 @print_mulacc(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) {
-; CHECK-LABEL: 'print_mulacc'
+; CHECK-LABEL: VPlan for loop in 'print_mulacc'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -473,7 +473,7 @@ exit:
}
define i64 @print_mulacc_extended(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) {
-; CHECK-LABEL: 'print_mulacc_extended'
+; CHECK-LABEL: VPlan for loop in 'print_mulacc_extended'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -562,7 +562,7 @@ exit:
}
define i64 @print_extended_sub_reduction(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) {
-; CHECK-LABEL: 'print_extended_sub_reduction'
+; CHECK-LABEL: VPlan for loop in 'print_extended_sub_reduction'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -638,7 +638,7 @@ exit:
}
define i32 @print_mulacc_sub(ptr %a, ptr %b) {
-; CHECK-LABEL: 'print_mulacc_sub'
+; CHECK-LABEL: VPlan for loop in 'print_mulacc_sub'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -724,7 +724,7 @@ exit:
}
define i32 @print_mulacc_negated(ptr %a, ptr %b) {
-; CHECK-LABEL: 'print_mulacc_negated'
+; CHECK-LABEL: VPlan for loop in 'print_mulacc_negated'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -812,7 +812,7 @@ exit:
}
define i64 @print_mulacc_sub_extended(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) {
-; CHECK-LABEL: 'print_mulacc_sub_extended'
+; CHECK-LABEL: VPlan for loop in 'print_mulacc_sub_extended'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -901,7 +901,7 @@ exit:
}
define i64 @print_mulacc_duplicate_extends(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) {
-; CHECK-LABEL: 'print_mulacc_duplicate_extends'
+; CHECK-LABEL: VPlan for loop in 'print_mulacc_duplicate_extends'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -981,7 +981,7 @@ exit:
}
define i32 @print_mulacc_extended_const(ptr %start, ptr %end) {
-; CHECK-LABEL: 'print_mulacc_extended_const'
+; CHECK-LABEL: VPlan for loop in 'print_mulacc_extended_const'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -1058,7 +1058,7 @@ exit:
}
define i32 @print_mulacc_extended_const_lhs(ptr %start, ptr %end) {
-; CHECK-LABEL: 'print_mulacc_extended_const_lhs'
+; CHECK-LABEL: VPlan for loop in 'print_mulacc_extended_const_lhs'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -1137,7 +1137,7 @@ exit:
; Constants >= 128 cannot be treated as sign-extended, so the expression shouldn't extend 128
define i32 @print_mulacc_not_extended_const(ptr %start, ptr %end) {
-; CHECK-LABEL: 'print_mulacc_not_extended_const'
+; CHECK-LABEL: VPlan for loop in 'print_mulacc_not_extended_const'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -1216,7 +1216,7 @@ exit:
}
define i64 @print_ext_mulacc_extended_const(ptr %start, ptr %end) {
-; CHECK-LABEL: 'print_ext_mulacc_extended_const'
+; CHECK-LABEL: VPlan for loop in 'print_ext_mulacc_extended_const'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -1296,7 +1296,7 @@ exit:
; Constants >= 128 cannot be treated as sign-extended, so the expression shouldn't extend 128
define i64 @print_ext_mulacc_not_extended_const(ptr %start, ptr %end) {
-; CHECK-LABEL: 'print_ext_mulacc_not_extended_const'
+; CHECK-LABEL: VPlan for loop in 'print_ext_mulacc_not_extended_const'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -1382,7 +1382,7 @@ exit:
; It can however be turned into an ExtendedReduction since that one doesn't
; modify the mul's operands.
define i64 @print_ext_mul_two_uses(i64 %n, ptr %a, i16 %b, i32 %c) {
-; CHECK-LABEL: 'print_ext_mul_two_uses'
+; CHECK-LABEL: VPlan for loop in 'print_ext_mul_two_uses'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF * UF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = vector-trip-count
@@ -1471,7 +1471,7 @@ exit:
}
define i32 @print_umax_reduction(ptr %y) {
-; CHECK-LABEL: 'print_umax_reduction'
+; CHECK-LABEL: VPlan for loop in 'print_umax_reduction'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
index c9a186cb3f1f8..143a039adf209 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
@@ -8,7 +8,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
; Tests for printing VPlans.
define void @print_call_and_memory(i64 %n, ptr noalias %y, ptr noalias %x) nounwind uwtable {
-; CHECK-LABEL: 'print_call_and_memory'
+; CHECK-LABEL: VPlan for loop in 'print_call_and_memory'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -82,7 +82,7 @@ for.end: ; preds = %for.body, %entry
}
define void @print_widen_gep_and_select(i64 %n, ptr noalias %y, ptr noalias %x, ptr %z) nounwind uwtable {
-; CHECK-LABEL: 'print_widen_gep_and_select'
+; CHECK-LABEL: VPlan for loop in 'print_widen_gep_and_select'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -163,7 +163,7 @@ for.end: ; preds = %for.body, %entry
}
define void @print_replicate_predicated_phi(i64 %n, ptr %x) {
-; CHECK-LABEL: 'print_replicate_predicated_phi'
+; CHECK-LABEL: VPlan for loop in 'print_replicate_predicated_phi'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -258,7 +258,7 @@ for.end: ; preds = %for.inc
@CD = common global [1024 x i32] zeroinitializer, align 4
define void @print_interleave_groups(i32 %C, i32 %D) {
-; CHECK-LABEL: 'print_interleave_groups'
+; CHECK-LABEL: VPlan for loop in 'print_interleave_groups'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -364,7 +364,7 @@ for.end:
}
define void @recipe_debug_loc_location(ptr nocapture %src) !dbg !5 {
-; CHECK-LABEL: 'recipe_debug_loc_location'
+; CHECK-LABEL: VPlan for loop in 'recipe_debug_loc_location'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -472,7 +472,7 @@ declare float @llvm.sqrt.f32(float) nounwind readnone
declare float @llvm.fmuladd.f32(float, float, float)
define void @print_expand_scev(i64 %y, ptr %ptr) {
-; CHECK-LABEL: 'print_expand_scev'
+; CHECK-LABEL: VPlan for loop in 'print_expand_scev'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -549,7 +549,7 @@ loop.exit:
}
define i32 @print_exit_value(ptr %ptr, i32 %off) {
-; CHECK-LABEL: 'print_exit_value'
+; CHECK-LABEL: VPlan for loop in 'print_exit_value'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -620,7 +620,7 @@ exit:
}
define void @print_fast_math_flags(i64 %n, ptr noalias %y, ptr noalias %x, ptr %z) {
-; CHECK-LABEL: 'print_fast_math_flags'
+; CHECK-LABEL: VPlan for loop in 'print_fast_math_flags'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -699,7 +699,7 @@ exit:
}
define void @print_exact_flags(i64 %n, ptr noalias %x) {
-; CHECK-LABEL: 'print_exact_flags'
+; CHECK-LABEL: VPlan for loop in 'print_exact_flags'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -775,7 +775,7 @@ exit:
}
define void @print_call_flags(ptr readonly %src, ptr noalias %dest, i64 %n) {
-; CHECK-LABEL: 'print_call_flags'
+; CHECK-LABEL: VPlan for loop in 'print_call_flags'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -877,7 +877,7 @@ end:
; FIXME: Preserve disjoint flag on OR recipe.
define void @print_disjoint_flags(i64 %n, ptr noalias %x) {
-; CHECK-LABEL: 'print_disjoint_flags'
+; CHECK-LABEL: VPlan for loop in 'print_disjoint_flags'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -953,7 +953,7 @@ exit:
}
define void @zext_nneg(ptr noalias %p, ptr noalias %p1) {
-; CHECK-LABEL: 'zext_nneg'
+; CHECK-LABEL: VPlan for loop in 'zext_nneg'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -1024,7 +1024,7 @@ exit:
}
define i16 @print_first_order_recurrence_and_result(ptr %ptr) {
-; CHECK-LABEL: 'print_first_order_recurrence_and_result'
+; CHECK-LABEL: VPlan for loop in 'print_first_order_recurrence_and_result'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
@@ -1103,7 +1103,7 @@ exit:
}
define void @print_select_with_fastmath_flags(ptr noalias %a, ptr noalias %b, ptr noalias %c, i64 %N) {
-; CHECK-LABEL: 'print_select_with_fastmath_flags'
+; CHECK-LABEL: VPlan for loop in 'print_select_with_fastmath_flags'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll b/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll
index 63c2d618bbd26..b8a8f386de376 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll
@@ -7,7 +7,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
; Make sure recipes with side-effects are not sunk.
define void @sink_with_sideeffects(i1 %c, ptr %ptr) {
-; CHECK-LABEL: 'sink_with_sideeffects'
+; CHECK-LABEL: VPlan for loop in 'sink_with_sideeffects'
; CHECK: VPlan 'Initial VPlan for VF={1},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
diff --git a/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll.expected b/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll.expected
index 970ba6afb567d..b33e0f149107b 100644
--- a/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll.expected
@@ -3,7 +3,7 @@
; RUN: -force-vector-width=4 -disable-output %s 2>&1 | FileCheck %s
define void @simple(ptr %p, i64 %n) {
-; CHECK-LABEL: 'simple'
+; CHECK-LABEL: VPlan for loop in 'simple'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
diff --git a/llvm/utils/UpdateTestChecks/common.py b/llvm/utils/UpdateTestChecks/common.py
index 5fcc056a4bb6d..78e36e8ddd090 100644
--- a/llvm/utils/UpdateTestChecks/common.py
+++ b/llvm/utils/UpdateTestChecks/common.py
@@ -2431,9 +2431,10 @@ def add_analyze_checks(
func_name,
ginfo: GeneralizerInfo,
is_filtered,
+ check_label_prefix=""
):
assert ginfo.is_analyze()
- check_label_format = "{} %s-LABEL: '%s%s%s%s'".format(comment_marker)
+ check_label_format = "{} %s-LABEL: {}'%s%s%s%s'".format(comment_marker, check_label_prefix)
global_vars_seen_dict = {}
return add_checks(
output_lines,
diff --git a/llvm/utils/update_analyze_test_checks.py b/llvm/utils/update_analyze_test_checks.py
index cc55f72425b16..a0139dcf7e1c0 100755
--- a/llvm/utils/update_analyze_test_checks.py
+++ b/llvm/utils/update_analyze_test_checks.py
@@ -128,6 +128,8 @@ def update_test(opt_basename: str, ti: common.TestInfo):
builder.processed_prefixes(prefixes)
+ check_label_prefix = "VPlan for loop in " if regex == common.VPLAN_RE else ""
+
func_dict = builder.finish_and_get_func_dict()
is_in_function = False
is_in_function_start = False
@@ -158,6 +160,7 @@ def update_test(opt_basename: str, ti: common.TestInfo):
func_name,
ginfo,
is_filtered=builder.is_filtered(),
+ check_label_prefix=check_label_prefix
)
)
is_in_function_start = False
>From c6813a29e7dce0ecf5ca2a915c376fcfdf03bc71 Mon Sep 17 00:00:00 2001
From: Andrei Elovikov <andrei.elovikov at sifive.com>
Date: Wed, 11 Feb 2026 08:56:51 -0800
Subject: [PATCH 5/5] Fix formatting
---
llvm/utils/UpdateTestChecks/common.py | 6 ++++--
llvm/utils/update_analyze_test_checks.py | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/llvm/utils/UpdateTestChecks/common.py b/llvm/utils/UpdateTestChecks/common.py
index 78e36e8ddd090..e0e3578a98faa 100644
--- a/llvm/utils/UpdateTestChecks/common.py
+++ b/llvm/utils/UpdateTestChecks/common.py
@@ -2431,10 +2431,12 @@ def add_analyze_checks(
func_name,
ginfo: GeneralizerInfo,
is_filtered,
- check_label_prefix=""
+ check_label_prefix="",
):
assert ginfo.is_analyze()
- check_label_format = "{} %s-LABEL: {}'%s%s%s%s'".format(comment_marker, check_label_prefix)
+ check_label_format = "{} %s-LABEL: {}'%s%s%s%s'".format(
+ comment_marker, check_label_prefix
+ )
global_vars_seen_dict = {}
return add_checks(
output_lines,
diff --git a/llvm/utils/update_analyze_test_checks.py b/llvm/utils/update_analyze_test_checks.py
index a0139dcf7e1c0..5329851e465e3 100755
--- a/llvm/utils/update_analyze_test_checks.py
+++ b/llvm/utils/update_analyze_test_checks.py
@@ -160,7 +160,7 @@ def update_test(opt_basename: str, ti: common.TestInfo):
func_name,
ginfo,
is_filtered=builder.is_filtered(),
- check_label_prefix=check_label_prefix
+ check_label_prefix=check_label_prefix,
)
)
is_in_function_start = False
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