[llvm] 00a8cb4 - [RISCV] Move NSRL/NSRA isel to tablegen. NFC (#181096)

[via llvm-commits]

Author: Craig Topper
Date: 2026-02-12T07:03:44-08:00
New Revision: 00a8cb4a6be8854408014eeac690b9aaf98cabff

URL: https://github.com/llvm/llvm-project/commit/00a8cb4a6be8854408014eeac690b9aaf98cabff
DIFF: https://github.com/llvm/llvm-project/commit/00a8cb4a6be8854408014eeac690b9aaf98cabff.diff

LOG: [RISCV] Move NSRL/NSRA isel to tablegen. NFC (#181096)

These nodes produce a single result so we can handle them in tablegen.

Assisted-by: claude

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    llvm/lib/Target/RISCV/RISCVInstrInfoP.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index b7dfd7e243382..db65d6ac1a5df 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1791,40 +1791,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     CurDAG->RemoveDeadNode(Node);
     return;
   }
-  case RISCVISD::NSRL:
-  case RISCVISD::NSRA: {
-    assert(Subtarget->hasStdExtP() && !Subtarget->is64Bit() && VT == MVT::i32 &&
-           "Unexpected opcode");
-
-    bool IsSRA = Node->getOpcode() == RISCVISD::NSRA;
-    SDValue Lo = Node->getOperand(0);
-    SDValue Hi = Node->getOperand(1);
-    SDValue ShAmt = Node->getOperand(2);
-
-    SDValue Ops[] = {
-        CurDAG->getTargetConstant(RISCV::GPRPairRegClassID, DL, MVT::i32), Lo,
-        CurDAG->getTargetConstant(RISCV::sub_gpr_even, DL, MVT::i32), Hi,
-        CurDAG->getTargetConstant(RISCV::sub_gpr_odd, DL, MVT::i32)};
-    SDValue Pair = SDValue(CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
-                                                  DL, MVT::Untyped, Ops),
-                           0);
-
-    MachineSDNode *Res;
-    if (auto *ShAmtC = dyn_cast<ConstantSDNode>(ShAmt)) {
-      unsigned Opc = IsSRA ? RISCV::NSRAI : RISCV::NSRLI;
-      Res = CurDAG->getMachineNode(
-          Opc, DL, MVT::i32, Pair,
-          CurDAG->getTargetConstant(*ShAmtC->getConstantIntValue(), DL,
-                                    MVT::i32));
-    } else {
-      // NSRL/NSRA only read 6 bits of the shift amount.
-      selectShiftMask(ShAmt, 64, ShAmt);
-      unsigned Opc = IsSRA ? RISCV::NSRA : RISCV::NSRL;
-      Res = CurDAG->getMachineNode(Opc, DL, MVT::i32, Pair, ShAmt);
-    }
-    ReplaceNode(Node, Res);
-    return;
-  }
   case ISD::LOAD: {
     if (tryIndexedLoad(Node))
       return;

diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index 19ee103af1425..eea041fe23432 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -89,6 +89,9 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
   bool selectShiftMask32(SDValue N, SDValue &ShAmt) {
     return selectShiftMask(N, 32, ShAmt);
   }
+  bool selectShiftMask64(SDValue N, SDValue &ShAmt) {
+    return selectShiftMask(N, 64, ShAmt);
+  }
 
   bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val);
   bool selectSETNE(SDValue N, SDValue &Val) {

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index e39e400f7d369..5d9a52644a38f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1504,6 +1504,13 @@ def SDT_RISCVNarrowingShift : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
 def riscv_nsrl : RVSDNode<"NSRL", SDT_RISCVNarrowingShift>;
 def riscv_nsra : RVSDNode<"NSRA", SDT_RISCVNarrowingShift>;
 
+// ComplexPattern for 64-bit shift mask (NSRL/NSRA only read 6 bits).
+def shiftMask64 : ComplexPattern<i32, 1, "selectShiftMask64", [], [], 0>;
+
+// Build a GPRPair from two GPR registers for narrowing shift instructions.
+def BuildGPRPair : OutPatFrag<(ops node:$lo, node:$hi),
+  (REG_SEQUENCE GPRPair, $lo, sub_gpr_even, $hi, sub_gpr_odd)>;
+
 // Averaging subtraction, (a - b) >> 2
 def riscv_asub : RVSDNode<"ASUB", SDTIntBinOp>;
 def riscv_asubu : RVSDNode<"ASUBU", SDTIntBinOp>;
@@ -1726,6 +1733,18 @@ let Predicates = [HasStdExtP, IsRV32] in {
   def : PatGprGpr<usubsat, SSUBU>;
   def : PatGprGpr<sshlsat, SSHA>;
 
+  // Narrowing shift patterns (NSRL/NSRA)
+  // Immediate shift amount patterns
+  def : Pat<(i32 (riscv_nsrl GPR:$lo, GPR:$hi, uimm6:$shamt)),
+            (NSRLI (BuildGPRPair GPR:$lo, GPR:$hi), uimm6:$shamt)>;
+  def : Pat<(i32 (riscv_nsra GPR:$lo, GPR:$hi, uimm6:$shamt)),
+            (NSRAI (BuildGPRPair GPR:$lo, GPR:$hi), uimm6:$shamt)>;
+  // Register shift amount patterns
+  def : Pat<(i32 (riscv_nsrl GPR:$lo, GPR:$hi, shiftMask64:$shamt)),
+            (NSRL (BuildGPRPair GPR:$lo, GPR:$hi), shiftMask64:$shamt)>;
+  def : Pat<(i32 (riscv_nsra GPR:$lo, GPR:$hi, shiftMask64:$shamt)),
+            (NSRA (BuildGPRPair GPR:$lo, GPR:$hi), shiftMask64:$shamt)>;
+
   // 8/16-bit multiply low patterns
   def: Pat<(v4i8 (mul GPR:$rs1, GPR:$rs2)),
            (PNSRLI_B (PWMUL_B GPR:$rs1, GPR:$rs2), 0)>;