[llvm] [GlobalISel] Add integer combines from SelectionDAG (PR #181126)

[Osman Yasar via llvm-commits]

https://github.com/osmanyasar05 updated https://github.com/llvm/llvm-project/pull/181126

>From 695bd43a8fd1f19fc906e72ba70938c3b6d92a13 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05 at gmail.com>
Date: Wed, 11 Feb 2026 21:24:07 +0000
Subject: [PATCH 1/2] first commit

---
 .../include/llvm/Target/GlobalISel/Combine.td | 16 +++++++
 .../AArch64/GlobalISel/combine-integer.mir    | 43 +++++++++++++++++++
 2 files changed, 59 insertions(+)

diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index f5c940bffc8fb..a90790afa8dfb 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -1946,6 +1946,20 @@ def APlusBMinusCPlusA : GICombineRule<
           (G_SUB $sub1, $B, $add1),
           (G_ADD $root, $A, $sub1)),
    (apply (G_SUB $root, $B, $C))>;
+  
+// fold (A - (0 - B)) to (A + B)
+def AMinusZeroMinusB : GICombineRule<
+   (defs root:$root),
+   (match (G_SUB $sub1, 0, $B),
+          (G_SUB $root, $A, $sub1)),
+   (apply (G_ADD $root, $A, $B))>;
+
+// fold A - (A - B) -> B
+def AMinusBMinusA: GICombineRule<
+   (defs root:$root),
+   (match (G_SUB $add, $A, $B),
+          (G_SUB $root, $A, $add)),
+   (apply (GIReplaceReg $root, $B))>;
 
 // fold (A+C1)-C2 -> A+(C1-C2)
 def APlusC1MinusC2: GICombineRule<
@@ -2008,6 +2022,8 @@ def integer_reassoc_combines: GICombineGroup<[
   AMinusBPlusBMinusC,
   APlusBMinusAplusC,
   APlusBMinusCPlusA,
+  AMinusZeroMinusB,
+  AMinusBMinusA,
   APlusC1MinusC2,
   C2MinusAPlusC1,
   AMinusC1MinusC2,
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
index c9b24ad75ce27..0f7efc9df34bb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
@@ -413,3 +413,46 @@ body:             |
     $x0 = COPY %add
     RET_ReallyLR implicit $x0
 
+...
+---
+name:   AMinusZeroMinusB
+body:             |
+  bb.0:
+    liveins: $w0, $w1
+
+
+    ; CHECK-LABEL: name: AMinusZeroMinusB
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %a:_(s64) = COPY $x0
+    ; CHECK-NEXT: %b:_(s64) = COPY $x1
+    ; CHECK-NEXT: %sub2:_(s64) = G_ADD %a, %b
+    ; CHECK-NEXT: $x0 = COPY %sub2(s64)
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
+    %a:_(s64) = COPY $x0
+    %b:_(s64) = COPY $x1
+    %c1:_(s64) = G_CONSTANT i64 0
+    %sub1:_(s64) = G_SUB %c1, %b
+    %sub2:_(s64) = G_SUB %a, %sub1
+    $x0 = COPY %sub2
+    RET_ReallyLR implicit $x0
+
+...
+---
+name:   AMinusBMinusA
+body:             |
+  bb.0:
+    liveins: $w0, $w1
+
+    ; CHECK-LABEL: name: AMinusBMinusA
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %b:_(s64) = COPY $x1
+    ; CHECK-NEXT: $x0 = COPY %b(s64)
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
+    %a:_(s64) = COPY $x0
+    %b:_(s64) = COPY $x1
+    %sub:_(s64) = G_SUB %a, %b
+    %add:_(s64) = G_SUB %a, %sub
+    $x0 = COPY %add
+    RET_ReallyLR implicit $x0

>From 82d53800751114ed96b3ee0f29f70c30e3b4ac25 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05 at gmail.com>
Date: Thu, 12 Feb 2026 12:56:58 +0000
Subject: [PATCH 2/2] modify tests

---
 llvm/test/CodeGen/AArch64/neg-selects.ll              |  4 +---
 .../test/CodeGen/AArch64/neon-bitwise-instructions.ll | 11 ++++-------
 2 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/llvm/test/CodeGen/AArch64/neg-selects.ll b/llvm/test/CodeGen/AArch64/neg-selects.ll
index b643ee7670e42..f656fc2e62040 100644
--- a/llvm/test/CodeGen/AArch64/neg-selects.ll
+++ b/llvm/test/CodeGen/AArch64/neg-selects.ll
@@ -35,9 +35,7 @@ define i32 @negneg_select_nega(i32 %a, i32 %b, i1 %bb) {
 ; CHECK-GI:       // %bb.0:
 ; CHECK-GI-NEXT:    and w8, w2, #0x1
 ; CHECK-GI-NEXT:    tst w8, #0x1
-; CHECK-GI-NEXT:    csneg w8, w1, w0, eq
-; CHECK-GI-NEXT:    neg w8, w8
-; CHECK-GI-NEXT:    neg w0, w8
+; CHECK-GI-NEXT:    csneg w0, w1, w0, eq
 ; CHECK-GI-NEXT:    ret
   %nega = sub i32 0, %a
   %sel = select i1 %bb, i32 %nega, i32 %b
diff --git a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
index 01aea72d77114..e8eb8e87f3b66 100644
--- a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
@@ -2849,14 +2849,11 @@ define <8 x i16> @pr149380(<4 x i16> %u1, <1 x i64> %u2, <8 x i16> %vqshlu_n169)
 ; CHECK-GI-LABEL: pr149380:
 ; CHECK-GI:       // %bb.0: // %entry
 ; CHECK-GI-NEXT:    movi v0.2d, #0xffffffffffffffff
-; CHECK-GI-NEXT:    neg v1.8h, v2.8h
-; CHECK-GI-NEXT:    movi v3.8h, #1
-; CHECK-GI-NEXT:    neg v1.8h, v1.8h
+; CHECK-GI-NEXT:    movi v1.8h, #1
 ; CHECK-GI-NEXT:    sub v0.8h, v0.8h, v2.8h
-; CHECK-GI-NEXT:    and v1.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT:    and v0.16b, v0.16b, v3.16b
-; CHECK-GI-NEXT:    orr v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT:    sqadd v0.8h, v3.8h, v0.8h
+; CHECK-GI-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT:    orr v0.16b, v2.16b, v0.16b
+; CHECK-GI-NEXT:    sqadd v0.8h, v1.8h, v0.8h
 ; CHECK-GI-NEXT:    ret
 entry:
   %mul.i = mul <8 x i16> %vqshlu_n169, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >