[llvm] [GlobalISel] Add sub_same_val rewrites from SelectionDAG (PR #181134)

Osman Yasar via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 12 04:47:30 PST 2026


https://github.com/osmanyasar05 created https://github.com/llvm/llvm-project/pull/181134

This PR adds the patterns `// Fold x op x -> 0` for `G_SUB` operation to GlobalISel. 

SelectionDAG rewrite: https://github.com/llvm/llvm-project/blob/838be78e44cd1f70006eb508bfc925e3e56aac03/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L4192


>From bc9b3a0ca9ab55c3ef9a7028c5f9138b5e47d385 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05 at gmail.com>
Date: Thu, 12 Feb 2026 12:32:35 +0000
Subject: [PATCH] add same_val rewrites

---
 .../include/llvm/Target/GlobalISel/Combine.td |  8 +++++++-
 .../AArch64/GlobalISel/combine-same-op.mir    | 20 +++++++++++++++++++
 2 files changed, 27 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/combine-same-op.mir

diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index f5c940bffc8fb..73b1869cb9deb 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -608,6 +608,12 @@ def binop_same_val: GICombineRule<
   (apply (GIReplaceReg $dst, $src))
 >;
 
+// fold (sub x, x) -> 0
+def sub_same_val: GICombineRule <
+  (defs root:$dst),
+  (match (G_SUB $dst, $x, $x)),
+  (apply (G_CONSTANT $dst, 0))>;
+
 // Fold (0 op x) - > 0
 def binop_left_to_zero_frags : GICombinePatFrag<
   (outs root:$dst, $zero), (ins $rhs),
@@ -2222,7 +2228,7 @@ def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
                                      insert_extract_vec_elt_out_of_bounds]>;
 
 def identity_combines : GICombineGroup<[select_same_val, right_identity_zero,
-                                        binop_same_val, binop_left_to_zero,
+                                        binop_same_val, sub_same_val, binop_left_to_zero,
                                         binop_right_to_zero, p2i_to_i2p,
                                         i2p_to_p2i, anyext_trunc_fold,
                                         fneg_fneg_fold, right_identity_one,
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-same-op.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-same-op.mir
new file mode 100644
index 0000000000000..a72ba0c7066f2
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-same-op.mir
@@ -0,0 +1,20 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+
+---
+name:            sub_same_op
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: sub_same_op
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s64) = COPY $x0
+    ; CHECK-NEXT: $x0 = COPY %x(s64)
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
+    %x:_(s64) = COPY $x0
+    %sub:_(s64) = G_SUB %x, %x
+    $x0 = COPY %sub
+    RET_ReallyLR implicit $x0



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