[llvm] AMDGPU/GlobalISel: Regbanklegalize rules for G_EXTRACT (PR #181036)

[Petar Avramovic via llvm-commits]

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@@ -644,6 +654,15 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Any({{UniBRC}, {{}, {}, VerifyAllSgpr}})
       .Any({{DivBRC}, {{}, {}, ApplyAllVgpr}});
 
+  addRulesForGOpcs({G_EXTRACT})
+      .Any({{UniS32, S64}, {{Sgpr32}, {Sgpr64}}})
+      .Any({{DivS32, S64}, {{Vgpr32}, {Vgpr64}}})
+      .Any({{UniS32, S1024}, {{Sgpr32}, {Sgpr1024}}})
+      .Any({{DivS32, S1024}, {{Vgpr32}, {Vgpr1024}}})
+      .Any({{DivP3}, {{VgprP3}, {VgprP0, Imm}}})
+      .Any({{DivP5, P0}, {{VgprP5}, {VgprP0, Imm}}})
+      .Any({{UniP6, P0}, {{SgprP6}, {SgprP0, Imm}}});
+
   Predicate isSignedICmp([](const MachineInstr &MI) -> bool {
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petar-avramovic wrote:

This should be much more generic (or is that other extract), it is really a sub-reg copy, so rule needs to support every type that matches size of some register class, the BRC
Also think it is worth writing Imm at the end of rules, just to make it obvious what it is extracting.


https://github.com/llvm/llvm-project/pull/181036