[llvm] [AMDGPU] Remove alignment constraint from spill pseudos (PR #177317)

[Matt Arsenault via llvm-commits]

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@@ -1536,12 +1536,21 @@ void SIRegisterInfo::buildSpillLoadStore(
   const bool IsAGPR = !ST.hasGFX90AInsts() && isAGPRClass(RC);
   const unsigned RegWidth = AMDGPU::getRegBitWidth(*RC) / 8;
 
+  // On targets with register tuple alignment requirements,
+  // for unaligned tuples, break the spill into 32-bit pieces.
+  // TODO: Optimize misaligned spills by using larger aligned chunks instead of
+  // 32-bit splits.
+  bool IsRegMisaligned = false;
+  if (ST.needsAlignedVGPRs() && IsFlat && !IsBlock && RegWidth > 4)
+    IsRegMisaligned = !isProperlyAlignedRC(*RC);
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arsenm wrote:

Yes 

https://github.com/llvm/llvm-project/pull/177317