[llvm] efab96c - [AMDGPU] Add missing assert requirement to unit test (#181102)

[via llvm-commits]

Author: Lucas Ramirez
Date: 2026-02-12T08:53:26Z
New Revision: efab96c6e9175af88666f6d8d7f7bf4c327d71b6

URL: https://github.com/llvm/llvm-project/commit/efab96c6e9175af88666f6d8d7f7bf4c327d71b6
DIFF: https://github.com/llvm/llvm-project/commit/efab96c6e9175af88666f6d8d7f7bf4c327d71b6.diff

LOG: [AMDGPU] Add missing assert requirement to unit test (#181102)

`-debug-only` is only available when asserts are enabled. The test
currently fails on builds without asserts.

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/misched-remat-revert.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AMDGPU/misched-remat-revert.ll b/llvm/test/CodeGen/AMDGPU/misched-remat-revert.ll
index 36df258ec5ab3..30f149de74e60 100644
--- a/llvm/test/CodeGen/AMDGPU/misched-remat-revert.ll
+++ b/llvm/test/CodeGen/AMDGPU/misched-remat-revert.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -O3 -debug-only=machine-scheduler 2>&1 < %s | FileCheck -check-prefix=DEBUG %s
+; REQUIRES: asserts
 
 ; This testcase hit a situation where reverting scheduling after the scheduler's
 ; rematerialization stage would cause incoherent MI and slot orders, hitting an