[llvm] [PowerPC] Legalize i8 for read/write global name registers (PR #180805)
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 11 09:04:01 PST 2026
https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/180805
>From d0b32d5183bd0ad74cf3d5b0e29745d393aef4b1 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Tue, 10 Feb 2026 13:33:28 -0500
Subject: [PATCH] Legalize i8 for rea/write global name registers
---
.../SelectionDAG/LegalizeIntegerTypes.cpp | 52 ++++++--
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 7 +
.../CodeGen/PowerPC/named-reg-alloc-i8.ll | 120 ++++++++++++++++++
3 files changed, 168 insertions(+), 11 deletions(-)
create mode 100644 llvm/test/CodeGen/PowerPC/named-reg-alloc-i8.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 4d08a22f25ab9..96253895e6290 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -2937,13 +2937,31 @@ SDValue DAGTypeLegalizer::PromoteIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
}
+/// Check if the target has set Promote action for the given register operation
+/// and type. Unlike isOperationLegalOrPromote, this works for illegal types.
+static bool hasPromoteActionForRegisterOp(const TargetLowering &TLI,
+ unsigned Opcode, EVT VT) {
+ return VT.isSimple() &&
+ TLI.getOperationAction(Opcode, VT.getSimpleVT()) ==
+ TargetLowering::Promote;
+}
+
SDValue DAGTypeLegalizer::PromoteIntOp_WRITE_REGISTER(SDNode *N,
unsigned OpNo) {
- const Function &Fn = DAG.getMachineFunction().getFunction();
- Fn.getContext().diagnose(DiagnosticInfoLegalizationFailure(
- "cannot use llvm.write_register with illegal type", Fn,
- N->getDebugLoc()));
- return N->getOperand(0);
+ assert(OpNo == 2 && "Unexpected operand number");
+ EVT VT = N->getOperand(2).getValueType();
+
+ if (!hasPromoteActionForRegisterOp(TLI, ISD::WRITE_REGISTER, VT)) {
+ const Function &Fn = DAG.getMachineFunction().getFunction();
+ Fn.getContext().diagnose(DiagnosticInfoLegalizationFailure(
+ "cannot use llvm.write_register with illegal type", Fn,
+ N->getDebugLoc()));
+ return N->getOperand(0);
+ }
+
+ SDValue Val = GetPromotedInteger(N->getOperand(2));
+ SmallVector<SDValue, 3> Ops = {N->getOperand(0), N->getOperand(1), Val};
+ return SDValue(DAG.UpdateNodeOperands(N, Ops), 0);
}
SDValue DAGTypeLegalizer::PromoteIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
@@ -6385,13 +6403,25 @@ SDValue DAGTypeLegalizer::PromoteIntRes_PATCHPOINT(SDNode *N) {
}
SDValue DAGTypeLegalizer::PromoteIntRes_READ_REGISTER(SDNode *N) {
- const Function &Fn = DAG.getMachineFunction().getFunction();
- Fn.getContext().diagnose(DiagnosticInfoLegalizationFailure(
- "cannot use llvm.read_register with illegal type", Fn, N->getDebugLoc()));
+ EVT VT = N->getValueType(0);
- EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- ReplaceValueWith(SDValue(N, 1), N->getOperand(0));
- return DAG.getPOISON(NVT);
+ if (!hasPromoteActionForRegisterOp(TLI, ISD::READ_REGISTER, VT)) {
+ const Function &Fn = DAG.getMachineFunction().getFunction();
+ Fn.getContext().diagnose(DiagnosticInfoLegalizationFailure(
+ "cannot use llvm.read_register with illegal type", Fn,
+ N->getDebugLoc()));
+ EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
+ ReplaceValueWith(SDValue(N, 1), N->getOperand(0));
+ return DAG.getPOISON(NVT);
+ }
+
+ SDLoc dl(N);
+ EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
+ SDValue Res = DAG.getNode(ISD::READ_REGISTER, dl,
+ DAG.getVTList(NVT, MVT::Other),
+ N->getOperand(0), N->getOperand(1));
+ ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
+ return Res;
}
SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 3c2ad1b30b139..9e9b36437a8c4 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -688,6 +688,13 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
+ // Legalize i8 for read/write global named registers.
+ setOperationAction(ISD::WRITE_REGISTER, MVT::i8, Promote);
+ setOperationAction(ISD::READ_REGISTER, MVT::i8, Promote);
+ MVT PromoteToVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
+ AddPromotedToType(ISD::WRITE_REGISTER, MVT::i8, PromoteToVT);
+ AddPromotedToType(ISD::READ_REGISTER, MVT::i8, PromoteToVT);
+
// Comparisons that require checking two conditions.
if (Subtarget.hasSPE()) {
setCondCodeAction(ISD::SETO, MVT::f32, Expand);
diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-i8.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-i8.ll
new file mode 100644
index 0000000000000..e3bf063e04689
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/named-reg-alloc-i8.ll
@@ -0,0 +1,120 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck %s
+; RUN: llc -O0 -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s --check-prefix=PPC64
+
+ at byteVal = dso_local global i8 15, align 1
+
+; Test writing i8 value to a named register
+define dso_local void @testSetByteReg(i8 noundef signext %val) nounwind {
+; CHECK-LABEL: testSetByteReg:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mr 5, 3
+; CHECK-NEXT: # kill: def $r3 killed $r5
+; CHECK-NEXT: blr
+;
+; PPC64-LABEL: testSetByteReg:
+; PPC64: # %bb.0: # %entry
+; PPC64-NEXT: mr 5, 3
+; PPC64-NEXT: blr
+entry:
+ tail call void @llvm.write_register.i8(metadata !0, i8 %val)
+ ret void
+}
+
+declare void @llvm.write_register.i8(metadata, i8)
+
+; Test reading i8 value from a named register
+define dso_local signext i8 @testGetByteReg() nounwind {
+; CHECK-LABEL: testGetByteReg:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stw 23, -36(1) # 4-byte Folded Spill
+; CHECK-NEXT: stw 24, -32(1) # 4-byte Folded Spill
+; CHECK-NEXT: stw 25, -28(1) # 4-byte Folded Spill
+; CHECK-NEXT: stw 26, -24(1) # 4-byte Folded Spill
+; CHECK-NEXT: stw 27, -20(1) # 4-byte Folded Spill
+; CHECK-NEXT: stw 28, -16(1) # 4-byte Folded Spill
+; CHECK-NEXT: stw 29, -12(1) # 4-byte Folded Spill
+; CHECK-NEXT: stw 30, -8(1) # 4-byte Folded Spill
+; CHECK-NEXT: stw 31, -4(1) # 4-byte Folded Spill
+; CHECK-NEXT: li 23, 42
+; CHECK-NEXT: extsb 3, 23
+; CHECK-NEXT: lwz 31, -4(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 30, -8(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 29, -12(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 28, -16(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 27, -20(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 26, -24(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 25, -28(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 24, -32(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 23, -36(1) # 4-byte Folded Reload
+; CHECK-NEXT: blr
+;
+; PPC64-LABEL: testGetByteReg:
+; PPC64: # %bb.0: # %entry
+; PPC64-NEXT: std 23, -72(1) # 8-byte Folded Spill
+; PPC64-NEXT: li 23, 42
+; PPC64-NEXT: extsb 3, 23
+; PPC64-NEXT: ld 23, -72(1) # 8-byte Folded Reload
+; PPC64-NEXT: blr
+entry:
+ tail call void @llvm.write_register.i8(metadata !1, i8 42)
+ %0 = tail call i8 @llvm.read_register.i8(metadata !1)
+ ret i8 %0
+}
+
+declare i8 @llvm.read_register.i8(metadata)
+
+; Test comparing i8 value from register with memory
+define dso_local signext i32 @testCmpByteReg() nounwind {
+; CHECK-LABEL: testCmpByteReg:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lwz 3, L..C0(2) # @byteVal
+; CHECK-NEXT: lbz 3, 0(3)
+; CHECK-NEXT: xori 3, 3, 15
+; CHECK-NEXT: cntlzw 3, 3
+; CHECK-NEXT: srwi 3, 3, 5
+; CHECK-NEXT: blr
+;
+; PPC64-LABEL: testCmpByteReg:
+; PPC64: # %bb.0: # %entry
+; PPC64-NEXT: addis 3, 2, byteVal at toc@ha
+; PPC64-NEXT: addi 3, 3, byteVal at toc@l
+; PPC64-NEXT: lbz 3, 0(3)
+; PPC64-NEXT: cmpwi 3, 15
+; PPC64-NEXT: crmove 20, 2
+; PPC64-NEXT: li 4, 0
+; PPC64-NEXT: li 3, 1
+; PPC64-NEXT: isel 3, 3, 4, 20
+; PPC64-NEXT: extsw 3, 3
+; PPC64-NEXT: blr
+entry:
+ tail call void @llvm.write_register.i8(metadata !0, i8 15)
+ %0 = load i8, ptr @byteVal, align 1
+ %1 = tail call i8 @llvm.read_register.i8(metadata !0)
+ %cmp = icmp eq i8 %0, %1
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+; Test zero-extending i8 from register
+define dso_local zeroext i8 @testZextByteReg(i8 noundef zeroext %val) nounwind {
+; CHECK-LABEL: testZextByteReg:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mr 5, 3
+; CHECK-NEXT: # kill: def $r3 killed $r5
+; CHECK-NEXT: clrlwi 3, 5, 24
+; CHECK-NEXT: blr
+;
+; PPC64-LABEL: testZextByteReg:
+; PPC64: # %bb.0: # %entry
+; PPC64-NEXT: mr 5, 3
+; PPC64-NEXT: clrldi 3, 5, 56
+; PPC64-NEXT: blr
+entry:
+ tail call void @llvm.write_register.i8(metadata !0, i8 %val)
+ %0 = tail call i8 @llvm.read_register.i8(metadata !0)
+ ret i8 %0
+}
+
+!0 = !{!"r5"}
+!1 = !{!"r23"}
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