[llvm] 14fe03f - [AArch64] Add extra fcmp+select tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 11 08:49:39 PST 2026
Author: David Green
Date: 2026-02-11T16:49:33Z
New Revision: 14fe03f6c6fd54f846860fa032fdb17ce190e98b
URL: https://github.com/llvm/llvm-project/commit/14fe03f6c6fd54f846860fa032fdb17ce190e98b
DIFF: https://github.com/llvm/llvm-project/commit/14fe03f6c6fd54f846860fa032fdb17ce190e98b.diff
LOG: [AArch64] Add extra fcmp+select tests. NFC
Some of these currently get scalarized with nnan.
Added:
Modified:
llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
index 8c8fde7934b89..f9f1d049b06d2 100644
--- a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
@@ -4219,3 +4219,525 @@ define <8 x i32> @fcmoeq8xfloat(<8 x float> %A, <8 x float> %B) {
%tmp4 = sext <8 x i1> %tmp3 to <8 x i32>
ret <8 x i32> %tmp4
}
+
+
+
+
+
+define <4 x float> @vselect_oeq(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-LABEL: vselect_oeq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: ret
+ %c = fcmp oeq <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ogt(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-LABEL: vselect_ogt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmgt v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: ret
+ %c = fcmp ogt <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_oge(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-LABEL: vselect_oge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmge v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: ret
+ %c = fcmp oge <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_olt(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-LABEL: vselect_olt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: ret
+ %c = fcmp olt <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ole(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-LABEL: vselect_ole:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmge v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: ret
+ %c = fcmp ole <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_one(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-LABEL: vselect_one:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmgt v4.4s, v0.4s, v1.4s
+; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: orr v0.16b, v0.16b, v4.16b
+; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: ret
+ %c = fcmp one <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ord(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-LABEL: vselect_ord:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmge v4.4s, v0.4s, v1.4s
+; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: orr v0.16b, v0.16b, v4.16b
+; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: ret
+ %c = fcmp ord <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ueq(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_ueq:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcmgt v4.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: orr v0.16b, v0.16b, v4.16b
+; CHECK-SD-NEXT: bsl v0.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_ueq:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmgt v4.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v4.16b
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp ueq <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ugt(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_ugt:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcmge v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: bsl v0.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_ugt:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmge v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp ugt <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_uge(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_uge:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: bsl v0.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_uge:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp uge <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ult(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_ult:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcmge v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: bsl v0.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_ult:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmge v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp ult <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ule(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_ule:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcmgt v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: bsl v0.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_ule:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmgt v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp ule <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_une(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_une:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: bsl v0.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_une:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmeq v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp une <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_uno(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_uno:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcmge v4.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: orr v0.16b, v0.16b, v4.16b
+; CHECK-SD-NEXT: bsl v0.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_uno:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmge v4.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v4.16b
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp uno <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_oeq_nnan(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-LABEL: vselect_oeq_nnan:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: ret
+ %c = fcmp nnan oeq <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ogt_nnan(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-LABEL: vselect_ogt_nnan:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmgt v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: ret
+ %c = fcmp nnan ogt <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_oge_nnan(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-LABEL: vselect_oge_nnan:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmge v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: ret
+ %c = fcmp nnan oge <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_olt_nnan(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_olt_nnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov s4, v1.s[1]
+; CHECK-SD-NEXT: mov s5, v0.s[1]
+; CHECK-SD-NEXT: fcmp s5, s4
+; CHECK-SD-NEXT: mov s4, v1.s[2]
+; CHECK-SD-NEXT: mov s5, v0.s[2]
+; CHECK-SD-NEXT: csetm w8, lt
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: mov s1, v1.s[3]
+; CHECK-SD-NEXT: mov s0, v0.s[3]
+; CHECK-SD-NEXT: csetm w9, lt
+; CHECK-SD-NEXT: fcmp s5, s4
+; CHECK-SD-NEXT: fmov s6, w9
+; CHECK-SD-NEXT: mov v6.s[1], w8
+; CHECK-SD-NEXT: csetm w8, lt
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: mov v6.s[2], w8
+; CHECK-SD-NEXT: csetm w8, lt
+; CHECK-SD-NEXT: mov v6.s[3], w8
+; CHECK-SD-NEXT: mov v0.16b, v6.16b
+; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_olt_nnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp nnan olt <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ole_nnan(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_ole_nnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov s4, v1.s[1]
+; CHECK-SD-NEXT: mov s5, v0.s[1]
+; CHECK-SD-NEXT: fcmp s5, s4
+; CHECK-SD-NEXT: mov s4, v1.s[2]
+; CHECK-SD-NEXT: mov s5, v0.s[2]
+; CHECK-SD-NEXT: csetm w8, le
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: mov s1, v1.s[3]
+; CHECK-SD-NEXT: mov s0, v0.s[3]
+; CHECK-SD-NEXT: csetm w9, le
+; CHECK-SD-NEXT: fcmp s5, s4
+; CHECK-SD-NEXT: fmov s6, w9
+; CHECK-SD-NEXT: mov v6.s[1], w8
+; CHECK-SD-NEXT: csetm w8, le
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: mov v6.s[2], w8
+; CHECK-SD-NEXT: csetm w8, le
+; CHECK-SD-NEXT: mov v6.s[3], w8
+; CHECK-SD-NEXT: mov v0.16b, v6.16b
+; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_ole_nnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmge v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp nnan ole <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_one_nnan(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_one_nnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: bsl v0.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_one_nnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmgt v4.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v4.16b
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp nnan one <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ord_nnan(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-LABEL: vselect_ord_nnan:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmge v4.4s, v0.4s, v1.4s
+; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: orr v0.16b, v0.16b, v4.16b
+; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: ret
+ %c = fcmp nnan ord <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ueq_nnan(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_ueq_nnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_ueq_nnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmgt v4.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v4.16b
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp nnan ueq <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ugt_nnan(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_ugt_nnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcmgt v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_ugt_nnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmge v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp nnan ugt <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_uge_nnan(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_uge_nnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcmge v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_uge_nnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp nnan uge <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ult_nnan(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_ult_nnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov s4, v1.s[1]
+; CHECK-SD-NEXT: mov s5, v0.s[1]
+; CHECK-SD-NEXT: fcmp s5, s4
+; CHECK-SD-NEXT: mov s4, v1.s[2]
+; CHECK-SD-NEXT: mov s5, v0.s[2]
+; CHECK-SD-NEXT: csetm w8, lt
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: mov s1, v1.s[3]
+; CHECK-SD-NEXT: mov s0, v0.s[3]
+; CHECK-SD-NEXT: csetm w9, lt
+; CHECK-SD-NEXT: fcmp s5, s4
+; CHECK-SD-NEXT: fmov s6, w9
+; CHECK-SD-NEXT: mov v6.s[1], w8
+; CHECK-SD-NEXT: csetm w8, lt
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: mov v6.s[2], w8
+; CHECK-SD-NEXT: csetm w8, lt
+; CHECK-SD-NEXT: mov v6.s[3], w8
+; CHECK-SD-NEXT: mov v0.16b, v6.16b
+; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_ult_nnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmge v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp nnan ult <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_ule_nnan(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_ule_nnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov s4, v1.s[1]
+; CHECK-SD-NEXT: mov s5, v0.s[1]
+; CHECK-SD-NEXT: fcmp s5, s4
+; CHECK-SD-NEXT: mov s4, v1.s[2]
+; CHECK-SD-NEXT: mov s5, v0.s[2]
+; CHECK-SD-NEXT: csetm w8, le
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: mov s1, v1.s[3]
+; CHECK-SD-NEXT: mov s0, v0.s[3]
+; CHECK-SD-NEXT: csetm w9, le
+; CHECK-SD-NEXT: fcmp s5, s4
+; CHECK-SD-NEXT: fmov s6, w9
+; CHECK-SD-NEXT: mov v6.s[1], w8
+; CHECK-SD-NEXT: csetm w8, le
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: mov v6.s[2], w8
+; CHECK-SD-NEXT: csetm w8, le
+; CHECK-SD-NEXT: mov v6.s[3], w8
+; CHECK-SD-NEXT: mov v0.16b, v6.16b
+; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_ule_nnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmgt v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp nnan ule <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_une_nnan(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_une_nnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: bsl v0.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_une_nnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmeq v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp nnan une <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
+
+define <4 x float> @vselect_uno_nnan(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {
+; CHECK-SD-LABEL: vselect_uno_nnan:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcmge v4.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: orr v0.16b, v0.16b, v4.16b
+; CHECK-SD-NEXT: bsl v0.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_uno_nnan:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcmge v4.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v4.16b
+; CHECK-GI-NEXT: mvn v0.16b, v0.16b
+; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ret
+ %c = fcmp nnan uno <4 x float> %a, %b
+ %r = select <4 x i1> %c, <4 x float> %d, <4 x float> %e
+ ret <4 x float> %r
+}
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